Module: Mesa Branch: master Commit: 52a800a687ee68483fe7cd83b137630b74e2127b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=52a800a687ee68483fe7cd83b137630b74e2127b
Author: Ilia Mirkin <[email protected]> Date: Tue Dec 1 15:01:11 2015 -0500 nv50/ir: allow immediate 0 to be loaded anywhere There's a post-RA fixup to replace 0's with $r63 (or $r127 if too many regs are used), so just as nvc0, let an immediate 0 be loaded anywhere. Signed-off-by: Ilia Mirkin <[email protected]> --- src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp index 94cf0f0..a0fb144 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_target_nv50.cpp @@ -268,6 +268,12 @@ TargetNV50::insnCanLoad(const Instruction *i, int s, { DataFile sf = ld->src(0).getFile(); + // immediate 0 can be represented by GPR $r63/$r127 + if (sf == FILE_IMMEDIATE && ld->getSrc(0)->reg.data.u64 == 0) + return (!i->isPseudo() && + !i->asTex() && + i->op != OP_EXPORT && i->op != OP_STORE); + if (sf == FILE_IMMEDIATE && (i->predSrc >= 0 || i->flagsDef >= 0)) return false; if (s >= opInfo[i->op].srcNr) _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
