Module: Mesa
Branch: master
Commit: 5e3edd4b2891d839d440f58053f7207fc71554f4
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e3edd4b2891d839d440f58053f7207fc71554f4

Author: Kenneth Graunke <[email protected]>
Date:   Thu Jan  7 15:45:21 2016 -0800

glsl: Make bitfield_insert/extract and bfi/bfm non-vectorizable.

Currently, opt_vectorize() tries to combine:

    result.x = bitfieldInsert(src0.x, src1.x, src2.x, src3.x);
    result.y = bitfieldInsert(src0.y, src1.y, src2.y, src3.y);
    result.z = bitfieldInsert(src0.z, src1.z, src2.z, src3.z);
    result.w = bitfieldInsert(src0.w, src1.w, src2.w, src3.w);

into a single ir_quadop_bitfield_insert opcode, which operates on
ivec4s.  However, GLSL IR's opcodes currently require the bits and
offset parameters to be scalar integers.  So, this breaks.

We want to be able to vectorize this eventually, but for now, just
chicken out and make opt_vectorize() bail by marking all the bitfield
insert/extract related opcodes as horizontal.  This is a relatively
uncommon case today, so we'll do the simple fix for stable branches,
and fix it properly on master.

Fixes assertion failures when compiling Shadow of Mordor vertex shaders
on i965 in vec4 mode (where OptimizeForAOS enables opt_vectorize()).

Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
Cc: [email protected]

---

 src/glsl/ir.h |    7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index a728c03..93e0734 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -1726,7 +1726,12 @@ public:
              operation == ir_binop_dot ||
              operation == ir_binop_vector_extract ||
              operation == ir_triop_vector_insert ||
-             operation == ir_quadop_vector;
+             operation == ir_quadop_vector ||
+             /* TODO: these can't currently be vectorized */
+             operation == ir_quadop_bitfield_insert ||
+             operation == ir_triop_bitfield_extract ||
+             operation == ir_triop_bfi ||
+             operation == ir_binop_bfm;
    }
 
    /**

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