Module: Mesa Branch: master Commit: 294ec530c9829aead97487b1feb06361ef97cc2d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=294ec530c9829aead97487b1feb06361ef97cc2d
Author: Marek Olšák <[email protected]> Date: Sat Jan 30 01:52:58 2016 +0100 gallium/radeon: just get num_tile_pipes from the winsys Reviewed-by: Michel Dänzer <[email protected]> --- src/gallium/drivers/radeon/r600_pipe_common.c | 34 --------------- src/gallium/drivers/radeon/r600_pipe_common.h | 1 - src/gallium/drivers/radeon/r600_texture.c | 6 +-- src/gallium/drivers/radeonsi/cik_sdma.c | 2 +- src/gallium/drivers/radeonsi/si_pipe.c | 52 ----------------------- src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 5 +++ 6 files changed, 9 insertions(+), 91 deletions(-) diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c index 849cc9b..e0c2469 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.c +++ b/src/gallium/drivers/radeon/r600_pipe_common.c @@ -803,23 +803,6 @@ static boolean r600_fence_finish(struct pipe_screen *screen, static bool r600_interpret_tiling(struct r600_common_screen *rscreen, uint32_t tiling_config) { - switch ((tiling_config & 0xe) >> 1) { - case 0: - rscreen->tiling_info.num_channels = 1; - break; - case 1: - rscreen->tiling_info.num_channels = 2; - break; - case 2: - rscreen->tiling_info.num_channels = 4; - break; - case 3: - rscreen->tiling_info.num_channels = 8; - break; - default: - return false; - } - switch ((tiling_config & 0x30) >> 4) { case 0: rscreen->tiling_info.num_banks = 4; @@ -847,23 +830,6 @@ static bool r600_interpret_tiling(struct r600_common_screen *rscreen, static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen, uint32_t tiling_config) { - switch (tiling_config & 0xf) { - case 0: - rscreen->tiling_info.num_channels = 1; - break; - case 1: - rscreen->tiling_info.num_channels = 2; - break; - case 2: - rscreen->tiling_info.num_channels = 4; - break; - case 3: - rscreen->tiling_info.num_channels = 8; - break; - default: - return false; - } - switch ((tiling_config & 0xf0) >> 4) { case 0: rscreen->tiling_info.num_banks = 4; diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h index 4e36631..0c44bd7 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.h +++ b/src/gallium/drivers/radeon/r600_pipe_common.h @@ -282,7 +282,6 @@ struct r600_surface { }; struct r600_tiling_info { - unsigned num_channels; unsigned num_banks; unsigned group_bytes; }; diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index ebafe3e..9d91e64 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -361,7 +361,7 @@ void r600_texture_get_cmask_info(struct r600_common_screen *rscreen, unsigned cmask_tile_elements = cmask_tile_width * cmask_tile_height; unsigned element_bits = 4; unsigned cmask_cache_bits = 1024; - unsigned num_pipes = rscreen->tiling_info.num_channels; + unsigned num_pipes = rscreen->info.num_tile_pipes; unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes; unsigned elements_per_macro_tile = (cmask_cache_bits / element_bits) * num_pipes; @@ -395,7 +395,7 @@ static void si_texture_get_cmask_info(struct r600_common_screen *rscreen, struct r600_cmask_info *out) { unsigned pipe_interleave_bytes = rscreen->tiling_info.group_bytes; - unsigned num_pipes = rscreen->tiling_info.num_channels; + unsigned num_pipes = rscreen->info.num_tile_pipes; unsigned cl_width, cl_height; switch (num_pipes) { @@ -515,7 +515,7 @@ static unsigned r600_texture_get_htile_size(struct r600_common_screen *rscreen, { unsigned cl_width, cl_height, width, height; unsigned slice_elements, slice_bytes, pipe_interleave_bytes, base_align; - unsigned num_pipes = rscreen->tiling_info.num_channels; + unsigned num_pipes = rscreen->info.num_tile_pipes; if (rscreen->chip_class <= EVERGREEN && rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 26) diff --git a/src/gallium/drivers/radeonsi/cik_sdma.c b/src/gallium/drivers/radeonsi/cik_sdma.c index 105a1b2..7691391 100644 --- a/src/gallium/drivers/radeonsi/cik_sdma.c +++ b/src/gallium/drivers/radeonsi/cik_sdma.c @@ -308,7 +308,7 @@ void cik_sdma_copy(struct pipe_context *ctx, } mtilew = (8 * rsrc->surface.bankw * - sctx->screen->b.tiling_info.num_channels) * + sctx->screen->b.info.num_tile_pipes) * rsrc->surface.mtilea; assert(!(mtilew & (mtilew - 1))); mtileh = (8 * rsrc->surface.bankh * num_banks) / diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 4ed8415..2599197 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -552,57 +552,6 @@ static void si_destroy_screen(struct pipe_screen* pscreen) r600_destroy_common_screen(&sscreen->b); } -#define SI_TILE_MODE_COLOR_2D_8BPP 14 - -/* Initialize pipe config. This is especially important for GPUs - * with 16 pipes and more where it's initialized incorrectly by - * the TILING_CONFIG ioctl. */ -static bool si_initialize_pipe_config(struct si_screen *sscreen) -{ - unsigned mode2d; - - /* This is okay, because there can be no 2D tiling without - * the tile mode array, so we won't need the pipe config. - * Return "success". - */ - if (!sscreen->b.info.si_tile_mode_array_valid) - return true; - - /* The same index is used for the 2D mode on CIK too. */ - mode2d = sscreen->b.info.si_tile_mode_array[SI_TILE_MODE_COLOR_2D_8BPP]; - - switch (G_009910_PIPE_CONFIG(mode2d)) { - case V_02803C_ADDR_SURF_P2: - sscreen->b.tiling_info.num_channels = 2; - break; - case V_02803C_X_ADDR_SURF_P4_8X16: - case V_02803C_X_ADDR_SURF_P4_16X16: - case V_02803C_X_ADDR_SURF_P4_16X32: - case V_02803C_X_ADDR_SURF_P4_32X32: - sscreen->b.tiling_info.num_channels = 4; - break; - case V_02803C_X_ADDR_SURF_P8_16X16_8X16: - case V_02803C_X_ADDR_SURF_P8_16X32_8X16: - case V_02803C_X_ADDR_SURF_P8_32X32_8X16: - case V_02803C_X_ADDR_SURF_P8_16X32_16X16: - case V_02803C_X_ADDR_SURF_P8_32X32_16X16: - case V_02803C_X_ADDR_SURF_P8_32X32_16X32: - case V_02803C_X_ADDR_SURF_P8_32X64_32X32: - sscreen->b.tiling_info.num_channels = 8; - break; - case V_02803C_X_ADDR_SURF_P16_32X32_8X16: - case V_02803C_X_ADDR_SURF_P16_32X32_16X16: - sscreen->b.tiling_info.num_channels = 16; - break; - default: - assert(0); - fprintf(stderr, "radeonsi: Unknown pipe config %i.\n", - G_009910_PIPE_CONFIG(mode2d)); - return false; - } - return true; -} - static bool si_init_gs_info(struct si_screen *sscreen) { switch (sscreen->b.family) { @@ -647,7 +596,6 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws) sscreen->b.b.resource_create = r600_resource_create_common; if (!r600_common_screen_init(&sscreen->b, ws) || - !si_initialize_pipe_config(sscreen) || !si_init_gs_info(sscreen)) { FREE(sscreen); return NULL; diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 3c8d5a7..b97ccfd 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -392,6 +392,11 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws) if (radeon_get_drm_value(ws->fd, RADEON_INFO_BACKEND_MAP, NULL, &ws->info.r600_gb_backend_map)) ws->info.r600_gb_backend_map_valid = TRUE; + } else { + ws->info.num_tile_pipes = + ws->info.chip_class >= EVERGREEN ? + 1 << (ws->info.r600_tiling_config & 0xf) : + 1 << ((ws->info.r600_tiling_config & 0xe) >> 1); } ws->info.has_virtual_memory = FALSE; _______________________________________________ mesa-commit mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/mesa-commit
