Module: Mesa Branch: master Commit: 10d84ba9f084174a1e8e7639dfb05dd855ba86e8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=10d84ba9f084174a1e8e7639dfb05dd855ba86e8
Author: Francisco Jerez <[email protected]> Date: Thu Jan 14 12:17:01 2016 -0800 i965: Invalidate state cache before L3 partitioning set-up. The state cache is also L3-backed so it seems sensible to make sure it's clean as we do for other RO caches before repartitioning the L3. This wasn't part of my original L3 partitioning code because I was able to reproduce hangs on Gen7 hardware when the state cache invalidation happened asynchronously with previous 3D rendering, which should no longer be possible after the previous change. Reviewed-by: Kenneth Graunke <[email protected]> --- src/mesa/drivers/dri/i965/gen7_l3_state.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c b/src/mesa/drivers/dri/i965/gen7_l3_state.c index 85f18d0..ff67c90 100644 --- a/src/mesa/drivers/dri/i965/gen7_l3_state.c +++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c @@ -355,6 +355,7 @@ setup_l3_config(struct brw_context *brw, const struct brw_l3_config *cfg) PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | PIPE_CONTROL_CONST_CACHE_INVALIDATE | PIPE_CONTROL_INSTRUCTION_INVALIDATE | + PIPE_CONTROL_STATE_CACHE_INVALIDATE | PIPE_CONTROL_NO_WRITE); /* Now send a third stalling flush to make sure that invalidation is _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
