Module: Mesa
Branch: vulkan
Commit: 8f3c23667433aacf5ad65a699c7ce082f3d6e416
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f3c23667433aacf5ad65a699c7ce082f3d6e416
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Thu Mar 24 13:05:04 2016 -0700
anv: Use genxml register support for L3 Cache config
The programming of the L3 Cache registers should match the previous
manually packed LRI values.
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
---
src/intel/vulkan/gen7_cmd_buffer.c | 53 +++++++++++++++++++++++---------------
src/intel/vulkan/gen8_cmd_buffer.c | 33 ++++++++++++------------
2 files changed, 48 insertions(+), 38 deletions(-)
diff --git a/src/intel/vulkan/gen7_cmd_buffer.c
b/src/intel/vulkan/gen7_cmd_buffer.c
index dbf05d0..04c1d3b 100644
--- a/src/intel/vulkan/gen7_cmd_buffer.c
+++ b/src/intel/vulkan/gen7_cmd_buffer.c
@@ -294,17 +294,10 @@ flush_compute_descriptor_set(struct anv_cmd_buffer
*cmd_buffer)
return VK_SUCCESS;
}
-static void
-emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
-{
- anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM),
- .RegisterOffset = reg,
- .DataDWord = imm);
-}
-
-#define GEN7_L3SQCREG1 0xb010
-#define GEN7_L3CNTLREG2 0xb020
-#define GEN7_L3CNTLREG3 0xb024
+#define emit_lri(batch, reg, imm) \
+ anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), \
+ .RegisterOffset = __anv_reg_num(reg), \
+ .DataDWord = imm)
void
genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, bool enable_slm)
@@ -315,12 +308,19 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer
*cmd_buffer, bool enable_slm)
* - src/mesa/drivers/dri/i965/gen7_l3_state.c
*/
- uint32_t l3c2_val = enable_slm ?
- /* All = 0 ways; URB = 16 ways; DC and RO = 16; SLM = 1 */
- /*0x02040021*/0x010000a1 :
- /* All = 0 ways; URB = 32 ways; DC = 0; RO = 32; SLM = 0 */
- /*0x04080040*/0x02000030;
- bool changed = cmd_buffer->state.current_l3_config != l3c2_val;
+ uint32_t l3cr2_slm, l3cr2_noslm;
+ anv_pack_struct(&l3cr2_noslm, GENX(L3CNTLREG2),
+ .URBAllocation = 24,
+ .ROAllocation = 0,
+ .DCAllocation = 16);
+ anv_pack_struct(&l3cr2_slm, GENX(L3CNTLREG2),
+ .SLMEnable = 1,
+ .URBAllocation = 16,
+ .URBLowBandwidth = 1,
+ .ROAllocation = 0,
+ .DCAllocation = 8);
+ const uint32_t l3cr2_val = enable_slm ? l3cr2_slm : l3cr2_noslm;
+ bool changed = cmd_buffer->state.current_l3_config != l3cr2_val;
if (changed) {
/* According to the hardware docs, the L3 partitioning can only be
changed
@@ -346,10 +346,21 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer
*cmd_buffer, bool enable_slm)
.CommandStreamerStallEnable = true);
anv_finishme("write GEN7_L3SQCREG1");
- emit_lri(&cmd_buffer->batch, GEN7_L3CNTLREG2, l3c2_val);
- emit_lri(&cmd_buffer->batch, GEN7_L3CNTLREG3,
- enable_slm ? 0x00040810 : 0x00040410);
- cmd_buffer->state.current_l3_config = l3c2_val;
+ emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG2), l3cr2_val);
+
+ uint32_t l3cr3_slm, l3cr3_noslm;
+ anv_pack_struct(&l3cr3_noslm, GENX(L3CNTLREG3),
+ .ISAllocation = 8,
+ .CAllocation = 4,
+ .TAllocation = 8);
+ anv_pack_struct(&l3cr3_slm, GENX(L3CNTLREG3),
+ .ISAllocation = 8,
+ .CAllocation = 8,
+ .TAllocation = 8);
+ const uint32_t l3cr3_val = enable_slm ? l3cr3_slm : l3cr3_noslm;
+ emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG3), l3cr3_val);
+
+ cmd_buffer->state.current_l3_config = l3cr2_val;
}
}
diff --git a/src/intel/vulkan/gen8_cmd_buffer.c
b/src/intel/vulkan/gen8_cmd_buffer.c
index 87b5e34..3fb5c27 100644
--- a/src/intel/vulkan/gen8_cmd_buffer.c
+++ b/src/intel/vulkan/gen8_cmd_buffer.c
@@ -108,15 +108,10 @@ gen8_cmd_buffer_emit_viewport(struct anv_cmd_buffer
*cmd_buffer)
}
#endif
-static void
-emit_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm)
-{
- anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM),
- .RegisterOffset = reg,
- .DataDWord = imm);
-}
-
-#define GEN8_L3CNTLREG 0x7034
+#define emit_lri(batch, reg, imm) \
+ anv_batch_emit(batch, GENX(MI_LOAD_REGISTER_IMM), \
+ .RegisterOffset = __anv_reg_num(reg), \
+ .DataDWord = imm)
void
genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, bool enable_slm)
@@ -127,12 +122,16 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer
*cmd_buffer, bool enable_slm)
* - src/mesa/drivers/dri/i965/gen7_l3_state.c
*/
- uint32_t val = enable_slm ?
- /* All = 48 ways; URB = 16 ways; DC and RO = 0, SLM = 1 */
- 0x60000021 :
- /* All = 48 ways; URB = 48 ways; DC, RO and SLM = 0 */
- 0x60000060;
- bool changed = cmd_buffer->state.current_l3_config != val;
+ uint32_t l3cr_slm, l3cr_noslm;
+ anv_pack_struct(&l3cr_noslm, GENX(L3CNTLREG),
+ .URBAllocation = 48,
+ .AllAllocation = 48);
+ anv_pack_struct(&l3cr_slm, GENX(L3CNTLREG),
+ .SLMEnable = 1,
+ .URBAllocation = 16,
+ .AllAllocation = 48);
+ const uint32_t l3cr_val = enable_slm ? l3cr_slm : l3cr_noslm;
+ bool changed = cmd_buffer->state.current_l3_config != l3cr_val;
if (changed) {
/* According to the hardware docs, the L3 partitioning can only be
changed
@@ -157,8 +156,8 @@ genX(cmd_buffer_config_l3)(struct anv_cmd_buffer
*cmd_buffer, bool enable_slm)
.PostSyncOperation = NoWrite,
.CommandStreamerStallEnable = true);
- emit_lri(&cmd_buffer->batch, GEN8_L3CNTLREG, val);
- cmd_buffer->state.current_l3_config = val;
+ emit_lri(&cmd_buffer->batch, GENX(L3CNTLREG), l3cr_val);
+ cmd_buffer->state.current_l3_config = l3cr_val;
}
}
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