Module: Mesa Branch: master Commit: 1f04d4bf59e753e2b199c247911520dc1fb30511 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f04d4bf59e753e2b199c247911520dc1fb30511
Author: Rob Clark <[email protected]> Date: Sat Apr 30 13:47:04 2016 -0400 freedreno/ir3: fix # of registers The instruction encoding allows for more registers, but at least on a3xx/a4xx they don't actually exist. Signed-off-by: Rob Clark <[email protected]> --- src/gallium/drivers/freedreno/ir3/ir3_ra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/freedreno/ir3/ir3_ra.c b/src/gallium/drivers/freedreno/ir3/ir3_ra.c index e0c3c80..f70c779 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_ra.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_ra.c @@ -98,7 +98,7 @@ static const unsigned half_class_sizes[] = { #define total_class_count (class_count + half_class_count) /* Below a0.x are normal regs. RA doesn't need to assign a0.x/p0.x. */ -#define NUM_REGS (4 * (REG_A0 - 1)) +#define NUM_REGS (4 * 48) /* Number of virtual regs in a given class: */ #define CLASS_REGS(i) (NUM_REGS - (class_sizes[i] - 1)) #define HALF_CLASS_REGS(i) (NUM_REGS - (half_class_sizes[i] - 1)) _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
