Module: Mesa Branch: master Commit: 08bcbfdc07ed6ba371998b00deb7a2a67357c6af URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=08bcbfdc07ed6ba371998b00deb7a2a67357c6af
Author: Marek Olšák <[email protected]> Date: Thu Sep 8 20:15:51 2016 +0200 radeonsi: flush TC L2 before using a compute indirect buffer There is no known test for this. Cc: 12.0 <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> --- src/gallium/drivers/radeonsi/si_compute.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_compute.c b/src/gallium/drivers/radeonsi/si_compute.c index f43c616..d988214 100644 --- a/src/gallium/drivers/radeonsi/si_compute.c +++ b/src/gallium/drivers/radeonsi/si_compute.c @@ -464,10 +464,18 @@ static void si_launch_grid( /* Add buffer sizes for memory checking in need_cs_space. */ r600_context_add_resource_size(ctx, &program->shader.bo->b.b); - if (info->indirect) - r600_context_add_resource_size(ctx, info->indirect); /* TODO: add the scratch buffer */ + if (info->indirect) { + r600_context_add_resource_size(ctx, info->indirect); + + /* The hw doesn't read the indirect buffer via TC L2. */ + if (r600_resource(info->indirect)->TC_L2_dirty) { + sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2; + r600_resource(info->indirect)->TC_L2_dirty = false; + } + } + si_need_cs_space(sctx); if (!sctx->cs_shader_state.initialized) _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
