Module: Mesa
Branch: master
Commit: 63193b9cdeca4f5d0e91f90c0926a1565f6b0415
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=63193b9cdeca4f5d0e91f90c0926a1565f6b0415

Author: Nicolai Hähnle <nicolai.haeh...@amd.com>
Date:   Fri Oct  7 16:15:30 2016 +0200

st/glsl_to_tgsi: disable on-the-fly peephole for 64-bit operations

This optimization is incorrect with 64-bit operations, because the
channel-splitting logic in emit_asm ends up being applied twice to
the source operands.

A lucky coincidence of how the writemask test works resulted in this
optimization basically never being applied anyway. As far as I can tell,
the only case where it would (incorrectly) have been applied is something
like

    dvec2 d;
    float x = (float)d.y;

which nobody seems to have ever done. But the moral equivalent does occur
in one of the component layout piglit test.

Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Edward O'Callaghan <funfunc...@folklore1984.net>
Reviewed-by: Dave Airlie <airl...@redhat.com>

---

 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 6a63e5c..dc20fe4 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -255,6 +255,7 @@ public:
    ir_instruction *ir;
    GLboolean cond_update;
    bool saturate;
+   bool is_64bit_expanded;
    st_src_reg sampler; /**< sampler register */
    int sampler_base;
    int sampler_array_size; /**< 1-based size of sampler array, 1 if not array 
*/
@@ -670,6 +671,7 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned 
op,
    inst->src[1] = src1;
    inst->src[2] = src2;
    inst->src[3] = src3;
+   inst->is_64bit_expanded = false;
    inst->ir = ir;
    inst->dead_mask = 0;
    /* default to float, for paths where this is not initialized
@@ -790,6 +792,7 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned 
op,
             dinst->prev = NULL;
          }
          this->instructions.push_tail(dinst);
+         dinst->is_64bit_expanded = true;
 
          /* modify the destination if we are splitting */
          for (j = 0; j < 2; j++) {
@@ -2908,6 +2911,7 @@ glsl_to_tgsi_visitor::visit(ir_assignment *ir)
    } else if (ir->rhs->as_expression() &&
               this->instructions.get_tail() &&
               ir->rhs == ((glsl_to_tgsi_instruction 
*)this->instructions.get_tail())->ir &&
+              !((glsl_to_tgsi_instruction 
*)this->instructions.get_tail())->is_64bit_expanded &&
               type_size(ir->lhs->type) == 1 &&
               l.writemask == ((glsl_to_tgsi_instruction 
*)this->instructions.get_tail())->dst[0].writemask) {
       /* To avoid emitting an extra MOV when assigning an expression to a

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