Module: Mesa
Branch: master
Commit: ec24f009caf60e47f772dc2cf66789fc464e30cf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec24f009caf60e47f772dc2cf66789fc464e30cf
Author: Rob Clark <robdcl...@gmail.com>
Date: Tue Dec 6 14:21:22 2016 -0500
freedreno/a5xx: gmem bypass mode
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
src/gallium/drivers/freedreno/a5xx/fd5_gmem.c | 72 +++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
index f505733..1b6b784 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
@@ -469,6 +469,77 @@ fd5_emit_tile_fini(struct fd_batch *batch)
fd5_set_render_mode(batch->ctx, batch->gmem, BYPASS);
}
+static void
+fd5_emit_sysmem_prep(struct fd_batch *batch)
+{
+ struct pipe_framebuffer_state *pfb = &batch->framebuffer;
+ struct fd_ringbuffer *ring = batch->gmem;
+
+ fd5_emit_restore(batch, ring);
+
+ OUT_PKT7(ring, CP_EVENT_WRITE, 1);
+ OUT_RING(ring, UNK_26);
+
+ OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
+ OUT_RING(ring, 0x0);
+
+ OUT_PKT4(ring, REG_A5XX_PC_POWER_CNTL, 1);
+ OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
+
+ OUT_PKT4(ring, REG_A5XX_VFD_POWER_CNTL, 1);
+ OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
+
+ /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
+ fd_wfi(batch, ring);
+ OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
+ OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */
+
+ OUT_PKT4(ring, REG_A5XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
+ OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_TL_X(0) |
+ A5XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(0));
+ OUT_RING(ring, A5XX_GRAS_SC_WINDOW_SCISSOR_BR_X(pfb->width - 1) |
+ A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(pfb->height - 1));
+
+ OUT_PKT4(ring, REG_A5XX_RB_RESOLVE_CNTL_1, 2);
+ OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_1_X(0) |
+ A5XX_RB_RESOLVE_CNTL_1_Y(0));
+ OUT_RING(ring, A5XX_RB_RESOLVE_CNTL_2_X(pfb->width - 1) |
+ A5XX_RB_RESOLVE_CNTL_2_Y(pfb->height - 1));
+
+ OUT_PKT4(ring, REG_A5XX_RB_WINDOW_OFFSET, 1);
+ OUT_RING(ring, A5XX_RB_WINDOW_OFFSET_X(0) |
+ A5XX_RB_WINDOW_OFFSET_Y(0));
+
+ OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
+ OUT_RING(ring, 0x1);
+
+ OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
+ OUT_RING(ring, A5XX_RB_CNTL_WIDTH(0) |
+ A5XX_RB_CNTL_HEIGHT(0) |
+ A5XX_RB_CNTL_BYPASS);
+
+ patch_draws(batch, IGNORE_VISIBILITY);
+
+ emit_zs(ring, pfb->zsbuf, NULL);
+ emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL);
+
+ // TODO MSAA
+ OUT_PKT4(ring, REG_A5XX_TPL1_TP_RAS_MSAA_CNTL, 2);
+ OUT_RING(ring, A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
+ OUT_RING(ring, A5XX_TPL1_TP_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
+ A5XX_TPL1_TP_DEST_MSAA_CNTL_MSAA_DISABLE);
+
+ OUT_PKT4(ring, REG_A5XX_RB_RAS_MSAA_CNTL, 2);
+ OUT_RING(ring, A5XX_RB_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
+ OUT_RING(ring, A5XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
+ A5XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE);
+
+ OUT_PKT4(ring, REG_A5XX_GRAS_SC_RAS_MSAA_CNTL, 2);
+ OUT_RING(ring, A5XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
+ OUT_RING(ring, A5XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
+ A5XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE);
+}
+
void
fd5_gmem_init(struct pipe_context *pctx)
{
@@ -480,4 +551,5 @@ fd5_gmem_init(struct pipe_context *pctx)
ctx->emit_tile_renderprep = fd5_emit_tile_renderprep;
ctx->emit_tile_gmem2mem = fd5_emit_tile_gmem2mem;
ctx->emit_tile_fini = fd5_emit_tile_fini;
+ ctx->emit_sysmem_prep = fd5_emit_sysmem_prep;
}
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