URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a83e9892dd4b3a1895ede1b2d3d5fac01d56dc3
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Jun 23 09:22:09 2016 +0200
i965/vec4: enable ARB_gpu_shader_fp64 for Haswell
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c350e34eefe483f03c4bd61ae9cbe7b3a66a246
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Sep 6 11:46:26 2016 +0200
i965/vec4: adjust spilling costs for 64-bit registers.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3cd38b68987f28536abd218fd62de5dc38c14aa1
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Sep 6 08:56:05 2016 +0200
i965/vec4: prevent spilling of DOUBLE_TO_SINGLE destination
FROM_DOUBLE opcodes are setup so that they use a dst register
with a size of 2 even if they only produce a single-precison
result (this is so that the opcode can use the larger register to
produce a 64-bit aligned intermediary result as required by the
hardware during the conversion process). This creates a problem for
spilling though, because when we attempt to emit a spill for the
dst we see a 32-bit destination and emit a scratch write that
allocates a single spill register, making the intermediary writes
go beyond the size of the allocation.
Prevent this by avoiding to spill the destination register of these
opcodes.
Alternatively, we can avoid this by splitting the opcode in two: one
that produces a 64-bit aligned result and one that takes the 64-bit
aligned result as input and produces a 32-bit result from it.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8843c43f7e85423b559383b38c77477139b4b06e
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Sep 9 12:21:06 2016 +0200
i965/vec4: avoid spilling of registers that mix 32-bit and 64-bit access
When 64-bit registers are (un)spilled, we need to execute data shuffling
code before writing to or after reading from memory. If we have instructions
that operate on 64-bit data via 32-bit instructions, (un)spills for the
register produced by 32-bit instructions will not do data shuffling at all
(because we only see a normal 32-bit istruction seemingly operating on
32-bit data). This means that subsequent reads with that register using DF
access will unshuffle data read from memory that was never adequately
shuffled when it was written.
Fixing this would require to identify which 32-bit instructions write
64-bit data and emit spill instructions only when the full 64-bit
data has been written (by multiple 32-bit instructions writing to different
offsets of the same register) and always emit 64-bit unspills whenever
64-bit data is read, even when the instruction uses a 32-bit type to read
from them.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=82c69426a5a32f9189c8b01059f831c84e9b83a3
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Sep 1 14:38:57 2016 +0200
i965/vec4: support basic spilling of 64-bit registers
The current spilling code can't spill vgrf allocations larger than 1
but SIMD4x2 doubles require 2 vgrfs, so we need to permit this case (which
is handled properly for DF data types by emitting 2 scratch messages and
doing data shuffling). We accomplish this by not auto-disabling spilling
for vgrf allocations with a size of 2, and then disable spilling on any
register with an offset != 0B (which indicates array access).
Disable spilling of partial DF reads/writes because these don't read/write
data for both logical threads and our scratch messages for 64-bit data
need data for both threads to be present.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c762809e49daf61fc986721006ce6a520e6e735f
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Sep 1 12:01:02 2016 +0200
i965/vec4: run scalarize_df() after spilling
Spilling of 64-bit data requires data shuffling for the corresponding
scratch read/write messages. This produces unsupported swizzle regions
and writemasks that we need to scalarize.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=73610384a8357287cef64434c789ff03c2f6f37a
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Sep 1 14:23:26 2016 +0200
i965/vec4: prevent src/dst hazards during 64-bit register allocation
8-wide compressed DF operations are executed as two separate 4-wide
DF operations. In that scenario, we have to be careful when we allocate
register space for their operands to prevent the case where the first
half of the instruction overwrites the source of the second half.
To do this we mark compressed instructions as having hazards to make
sure that ther register allocators assigns a register regions for the
destination that does not overlap with the region assigned for any
of its source operands.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b57adad0056273e38d9a9736cd98be95c0deb07
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Aug 18 11:15:56 2016 +0200
i965/vec4/scalarize_df: support more swizzles via vstride=0
By exploiting gen7's hardware decompression bug with vstride=0 we gain the
capacity to support additional swizzle combinations.
This also fixes ZW writes from X/Y channels like in:
mov r2.z:df r0.xxxx:df
Because DF regions use 2-wide rows with a vstride of 2, the region generated
for the source would be r0<2,2,1>.xyxy:DF, which is equivalent to r0.xxzz,
so
we end up writing r0.z in r2.z instead of r0.x. Using a vertical stride of 0
in these cases we get to replicate the XX swizzle and write what we want.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c3edacaa288ae01c0f37e645737feeeb48f2c3f2
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Jul 19 09:28:04 2016 +0200
i965/vec4/scalarize_df: do not scalarize swizzles that we can support
natively
Certain swizzles like XYZW can be supported by translating only the first
two
64-bit swizzle channels to 32-bit channels. This happens with swizzles such
that the first two logical components, when translated to 32-bit channels
and
replicated across the second dvec2 row, select the same channels specified
by
the 3rd and 4th logical swizzle components.
Notice that this opens up the possibility that some instructions are not
scalarized and can end up with XY or ZW 32-bit writemasks. Make sure we
always
scalarize in such cases.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f0bc54e2bf6c7d218f30acc88f5cb94bd6214f7
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Jul 1 09:26:32 2016 +0200
i965/vec4: split instructions that read 64-bit interleaved attributes
Stages that use interleaved attributes generate regions with a vstride=0
that can hit the gen7 hardware decompression bug.
v2:
- Make static the function and fix indent (Matt)
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0579c85e5ca7d406cad42db7c1501d6b1fb9696b
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Jul 1 09:28:31 2016 +0200
i965/vec4: dump subnr for FIXED_GRF
This came in handy when debugging the payload setup for Tess Eval,
since it prints correct subnr for attributes that can be loaded
in the second half of a register.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e92b402030735edab6c35e69dceee4acebb973b
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Sep 15 10:49:40 2016 +0200
i965/vec4/tes: consider register offsets during attribute setup
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=49d4d0268bc03fbf2a0688563c5d89a7c9eb1e8e
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Jul 1 09:22:34 2016 +0200
i965/vec4/tes: fix setup_payload() for 64bit data types
Use a width of 2 with 64-bit attributes.
Also, if we have a dvec3/4 attribute that gets split across two registers
such that components XY are stored in the second half of a register and
components ZW are stored in the first half of the next, we need to fix
regioning for any instruction that reads components Z/W of the attribute.
Notice this also means that we can't support sources that read cross-dvec2
swizzles (like XZ for example).
v2: don't assert that we have a single channel swizzle in the case that we
have to fix up Z/W access on the first half of the next register. We
can handle any swizzle that does not cross dvec2 boundaries, which
the double scalarization pass should have prevented anyway.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=183cd8ab944c1a6667656bed54a43ad5f91a6006
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Jul 1 09:24:12 2016 +0200
i965/vec4/tes: fix input loading for 64bit data types
v2: use byte_offset() instead of offset()
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e294ab8931296999e2cabdd7b1817f9a461beca
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Jun 30 11:03:17 2016 +0200
i965/vec4/tcs: fix outputs for 64-bit data
v2: use byte_offset() instead of offset()
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=639e92ea3cd62c458318029b0b378ac0177e5bd4
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Jul 1 11:35:06 2016 +0200
i965/vec4/tcs: fix input loading for 64-bit data
v2: use byte_offset() instead of offset()
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=74fd0c590b33a1975933367f814f98dcdc19b24e
Author: Samuel Iglesias Gonsálvez <[email protected]>
Date: Fri Jul 1 11:37:56 2016 +0200
i965/vec4/gs: fix input loading for 64bit data
v2 (Iago):
- Adapt 64-bit path to component packing changes.
Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]>
Signed-off-by: Iago Toral Quiroga <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b76f2206f550c37835d4e19eea1588caa0211b85
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Jul 1 09:01:56 2016 +0200
i965/vec4: fix store output for 64-bit types
We need to shuffle the data before it is written to the URB. Also,
dvec3/4 need two vec4 slots.
v2: use byte_offset() instead of offset().
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5fe8d567d8dadeb2b77addd73762f6bde4acfac2
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Oct 6 10:25:13 2016 +0200
i965/vec4: fix attribute setup for doubles
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a01259d8a13aace16e4f1ce9e09e0e41bd52273
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Oct 6 09:57:31 2016 +0200
i965/vec4: fix indentation in lower_attributes_to_hw_regs()
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae400e38d90ea2fddf1b050ff94f52bdec94e150
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Jul 15 13:02:27 2016 +0200
i965/vec4: make emit_pull_constant_load support 64-bit loads
This way callers don't need to know about 64-bit particularities and
we reuse some code.
v2:
- use byte_offset() instead of offset()
- only mark the surface as used once
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=df6e3aa6ae23346bad59d071d340a67be0e2a2c5
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Jul 13 10:45:13 2016 +0200
i965/vec4: fix move_push_constants_to_pull_constants() for 64-bit data
v2: adapt to changes in offset()
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eee2c0d7854e55e92e0e72eb0fb94ab83d702754
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Jul 13 10:21:18 2016 +0200
i965/vec4: fix indentation in move_push_constants_to_pull_constants()
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=10694be522cfc408dbbe3de3321be59c491408f6
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Jun 29 08:41:11 2016 +0200
i965/vec4: fix move_uniform_array_access_to_pull_constant() for 64-bit data
v2: adapt to changes in offset()
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=52fb22b64678b1dc855cffc9998103b31890a0c5
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Jun 28 12:03:09 2016 +0200
i965/vec4: fix scratch writes for 64bit data
Mostly the same stuff as usual: we ned to shuffle the data before we
write and we need to emit two 32-bit write messages (with appropriate
32-bit writemask channels set) for a full dvec4 scratch write.
v2: use byte_offset() instead of offset().
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dcc36f8b29ebc15ac4a8077e0902bf87c1de581c
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Jun 28 12:02:24 2016 +0200
i965/vec4: fix scratch reads for 64bit data
v2: Setup for a 64-bit scratch read by checking the type size of the
correct register
v3: Use byte_offset() instead of offset()
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e4d9ab609f217bde95722e76a98d646890c9abc9
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Feb 17 10:05:02 2016 +0100
i965/vec4: fix scratch offset for 64bit data
A vec4 is 16 bytes and a dvec4 is 32 bytes so for doubles we have
to multiply the reladdr by 2. The reg_offset part is in units of 16
bytes and is used to select the low/high 16-byte chunk of a full
dvec4, so we don't want to multiply that part of the address.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=07bc6a35d3d6d94d45b81bd10002f0e420d855c2
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Jun 28 11:54:07 2016 +0200
i965/vec4: do not split scratch read/write opcodes
64-bit scratch read/writes require to shuffle data around so we need
to have access to the full 64-bit data. We will do the right thing
for these when we emit the messages.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a857104e41167cef3c6a5132a45c88056c75dff
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Jun 23 10:40:47 2016 +0200
i965/vec4: Do not use DepCtrl with 64-bit instructions
The BDW PRM says that it is not supported, but it seems that gen7 is also
affected, since doing DepCtrl on double-float instructions leads to
GPU hangs in some cases, which is probably not surprising knowing that
this is not supported in new hardware iterations. The SKL PRMs do not
mention this restriction, so it is probably fine.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=506154f704dcb9185dadcd655fd6d0603916ea97
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Jun 23 10:35:50 2016 +0200
i965/vec4: extend the DWORD multiply DepCtrl restriction to all gen8
platforms
v2:
- Add Broxton as Intel's internal PRMs says that it is needed (Matt).
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9cd3f5b493e6fe835f1a3a2216f29bc0a4a2a93
Author: Samuel Iglesias Gonsálvez <[email protected]>
Date: Wed Jun 22 15:13:45 2016 +0200
i965/vec4: don't copy propagate misaligned registers
This means we would copy propagate partial reads or writes and that can
affect
the result.
Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=93eae0d2a4157963638130b7ea2ad656f366e372
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Jul 13 09:11:35 2016 +0200
i965/vec4: don't propagate single-precision uniforms into 4-wide
instructions
Otherwise we end up producing code that violates the register region
restriction that says that when execsize == width and hstride != 0
the vstride can't be 0.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6637312847527783eff9e315362ccd8cc87f595d
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Jun 23 08:34:53 2016 +0200
i965/vec4: Prevent copy propagation from violating pre-gen8 restrictions
In gen < 8 instructions that write more than one register need to read
more than one register too. Make sure we don't break that restriction
by copy propagating from a uniform.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=70cc6b0a022c1bfd8d17d5e931b276cb2ef2a456
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Jun 16 13:41:48 2016 +0200
i965/vec4: prevent copy-propagation from values with a different type size
Because the meaning of the swizzles and writemasks involved is different,
so replacing the source would lead to different semantics.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0fec5e9867fe46c543509f6555d31b8ada835f8e
Author: Connor Abbott <[email protected]>
Date: Thu Aug 13 15:44:14 2015 -0700
i965/vec4: don't constant propagate 64-bit immediates
v2: Also check if the instruction source target is 64-bit. (Samuel)
Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8eea41e75d86bfe9bef5f69b25ad797da236a008
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Feb 12 14:05:11 2016 +0100
i965/vec4: Fix SSBO stores for 64-bit data
In this case we need to shuffle the 64-bit data before we write it
to memory, source from reg_offset + 1 to write components Z and W
and consider that each DF channel is twice as big.
v2: use byte_offset() instead of offset().
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9998d55afd179ad5019d3841e4c3255a02fd2d7b
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Jul 13 13:34:55 2016 +0200
i965/vec4: Fix SSBO loads for 64-bit data
Same requirements as for UBO loads.
v2:
- use byte_offset() instead of offset() (Iago)
- keep the const. offset as an immediate like the original code did (Juan)
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4486c90aaeb08f424ce17f842f46d24d1ceaadcb
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Jul 13 12:10:18 2016 +0200
i965/vec4: Fix UBO loads for 64-bit data
We need to emit 2 32-bit load messages to load a full dvec4. If only
1 or 2 double components are needed dead-code-elimination will remove
the second one.
We also need to shuffle the result of the 32-bit messages to form
valid 64-bit SIMD4x2 data.
v2:
- use byte_offset() instead of offset() (Iago)
- keep the const. offset as an immediate like the original code did (Juan)
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8e123cc5d66022069f3aee53318bfd1075bcc53
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Jun 22 11:44:15 2016 +0200
i965/vec4: Add a shuffle_64bit_data helper
SIMD4x2 64bit data is stored in register space like this:
r0.0:DF x0 y0 z0 w0
r1.0:DF x1 y1 z1 w1
When we need to write data such as this to memory using 32-bit write
messages we need to shuffle it in this fashion:
r0.0:DF x0 y0 x1 y1
r0.1:DF z0 w0 z1 w1
and emit two 32-bit write messages, one for r0.0 at base_offset
and another one for r0.1 at base_offset+16.
We also need to do the inverse operation when we read using 32-bit messages
to produce valid SIMD4x2 64bit data from the data read. We can achieve this
by aplying the exact same shuffling to the data read, although we need to
apply different channel enables since the layout of the data is reversed.
This helper implements the data shuffling logic and we will use it in
various places where we read and write 64bit data from/to memory.
v2 (Curro):
- Use the writemask helper and don't assert on the original writemask
being XYZW.
- Use the Vec4 IR builder to simplify the implementation.
v3 (Iago):
- Use byte_offset() instead of offset().
v3:
- Fix typo (Matt)
- Clarify the example and fix indention (Matt).
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=017c8df35b343de0bb23220d030089bf57fb28d4
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Sep 28 13:03:00 2016 +0200
i965/vec4: support multiple dispatch widths and groups in the IR builder.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3a7d0ee9d5f792ab68fbe77da5e3ea85d4bc4c0
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Jun 8 11:04:34 2016 +0200
i965/vec4: Lower 64-bit MAD
The previous patch made sure that we do not generate MAD instructions
for any NIR's 64-bit ffma, but there is nothing preventing i965 from
producing MAD instructions as a result of lowerings or optimization
passes. This patch makes sure that any 64-bit MAD produced inside the
driver after translating from NIR is also converted to MUL+ADD before
we generate code.
v2:
- Use a copy constructor to copy all relevant instruction fields from
the original mad into the add and mul instructions
v3:
- Rename the lowering and fix commit log (Matt)
Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=82e9dda8bf8875d232840585f48763c7a7092918
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Jun 8 11:05:51 2016 +0200
i965/vec4/nir: do not emit 64-bit MAD
RepCtrl=1 does not work with 64-bit operands so we need to use RepCtrl=0.
In that situation, the regioning generated for the sources seems to be
equivalent to <4,4,1>:DF, so it will only work for components XY, which
means that we have to move any other swizzle to a temporary so that we can
source from channel X (or Y) in MAD and we also need to split the
instruction
(we are already scalarizing DF instructions but there is room for
improvement and with MAD would be more restricted in that area)
Also, it seems that MAD operations like this only write proper output for
channels X and Y, so writes to Z and W also need to be done to a temporary
using channels X/Y and then move that to channels Z or W of the actual dst.
As a result the code we produce for native 64-bit MAD instructions is rather
bad, and much worse than just emitting MUL+ADD. For reference, a simple case
of a fully scalarized dvec4 MAD operation requires 15 instructions if we use
native MAD and 8 instructions if we emit ADD+MUL instead. There are some
improvements that we can do to the emission of MAD that might bring the
instruction count down in some cases, but it comes at the expense of a more
complex implementation so it does not seem worth it, at least initially.
This patch makes translation of NIR's 64-bit FMMA instructions produce
MUL+ADD
instead of MAD. Currently, there is nothing else in the vec4 backend that
emits
MAD instructions, so this is sufficient and it helps optimization passes see
MUL+ADD from the get go.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=83dcd146020f5e54d1e0a46c585ed672e75abaa0
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Jun 1 08:35:37 2016 +0200
i965/vec4: Skip swizzle to subnr in 3src instructions with DF operands
We make scalar sources in 3src instructions use subnr instead of
swizzles because they don't really use swizzles.
With doubles it is more complicated because we use vstride=0 in
more scenarios in which they don't produce scalar regions. Also
RepCtrl=1 is not allowed with 64-bit operands, so we should avoid
this.
v2: Fix typo (Matt)
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=49be3abbe7afd64f9e3435e9a9e341e30acacb52
Author: Iago Toral Quiroga <[email protected]>
Date: Mon May 30 09:08:04 2016 +0200
i965/vec4: fix indentation in pack_uniform_registers
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bdf5498c6b7870c14139279e76f1e4b281bed2cd
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Jun 29 10:49:47 2016 +0200
i965/vec4: fix pack_uniform_registers for doubles
We need to consider the fact that dvec3/4 require two vec4 slots.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=23278a75ce06c3c083892b2a20d9efdf794167d6
Author: Iago Toral Quiroga <[email protected]>
Date: Mon Jul 18 12:04:13 2016 +0200
i965/vec4: teach register coalescing about 64-bit
Specifically, at least for now, we don't want to deal with the fact that
channel sizes for fp64 instructions are twice the size, so prevent
coalescing from instructions with a different type size.
Also, we should check that if we are coalescing a register from another
MOV we should be writing the same amount of data in both operations,
otherwise
we end up wiring more or less than the original instruction. This can
happen,
for example, when we have split fp64 MOVs with an exec size of 4 that only
write one register each and then a MOV with exec size of 8 that reads both.
We want to avoid the pass to think that it can coalesce from the first split
MOV alone. Ideally we would like the pass to see that it can coalesce from
both
split MOVs instead, but for now we keep it simple.
Finally, the pass doesn't support coalescing of multiple registers but in
the
case of normal SIMD4x2 double-precision instructions they naturally write
two
registers (one per vertex) and there is no reason why we should not allow
coalescing in this case. Change the restriction to bail if we see
instructions
that write more than 8 channels, where the channels can be 32-bit or 64-bit.
v2:
- Make sure that scan_inst and inst write the same amount of data.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c5bf597ef6eb4a33c9ba24827a34cd9fdd67363
Author: Iago Toral Quiroga <[email protected]>
Date: Wed May 25 14:29:39 2016 +0200
i965/disasm: fix subreg for dst in Align16 mode
There is a single bit for this, so it is a binary 0 or 1 meaning
offset 0B or 16B respectively.
v2:
- Since brw_inst_dst_da16_subreg_nr() is known to be 1, remove it
from the expression (Curro)
Reviewed-by: Francisco Jerez <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac5a06ff83c32ab14e01e526e729b2fbfe3a2426
Author: Iago Toral Quiroga <[email protected]>
Date: Mon Jul 18 13:43:00 2016 +0200
i965/vec4: implement access to DF source components Z/W
The general idea is that with 32-bit swizzles we cannot address DF
components Z/W directly, so instead we select the region that starts
at the the 16B offset into the register and use X/Y swizzles.
The above, however, has the caveat that we can't do that without
violating register region restrictions unless we probably do some
sort of SIMD splitting.
Alternatively, we can accomplish what we need without SIMD splitting
by exploiting the gen7 hardware decompression bug for instructions
with a vstride=0. For example, an instruction like this:
mov(8) r2.x:DF r0.2<0>xyzw:DF
Activates the hardware bug and produces this region:
Component: x0 y0 z0 w0 x1 y1 z1 w1
Register: r0.2 r0.3 r0.2 r0.3 r1.2 r1.3 r1.2 r1.3
Where r0.2 and r0.3 are r0.z:DF for the first vertex of the SIMD4x2
execution and r1.2 and r1.3 are the same for the second vertex.
Using this to our advantage we can select r0.z:DF by doing
r0.2<0,2,1>.xyxy and r0.w by doing r0.2<0,2,1>.zwzw without needing
to split the instruction.
Of course, this only works for gen7, but that is the only hardware
platform were we implement align16/fp64 at the moment.
v2: Adapted to the fact that we now do this after converting to
hardware registers (Iago)
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e238601a2da9512c0fd263e8378f30498a0a1507
Author: Iago Toral Quiroga <[email protected]>
Date: Tue May 24 11:01:27 2016 +0200
i965/vec4: translate 64-bit swizzles to 32-bit
The hardware can only operate with 32-bit swizzles, which is a rather
limiting restriction. However, the idea is not to expose this to the
optimization passes, which would be a mess to deal with. Instead, we let
the bulk of the vec4 backend ignore this fact and we fix the swizzles right
at codegen time.
At the moment the pass only needs to handle single value swizzles thanks to
the scalarization pass that runs before it.
Notice that this only works for X/Y swizzles. We will add support for Z/W
swizzles in the next patch, since they need a bit more work.
v2 (Sam):
- Do not expand swizzle of 64-bit immediate values.
v3:
- Do this after translation to hardware registers instead of doing it
right
before so we don't need the force_vstride0 flag (Curro).
- Squashed patch that included FIXED_GRF in the list of register files
that
need this translation (Iago).
- Remove swizzle assignments for VGRF and UNIFORM files in
convert_to_hw_regs(), they will be set by apply_logical_swizzle()
(Iago).
Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb7cb853c964db44ab99c1592e1ef7dec2f0c25b
Author: Iago Toral Quiroga <[email protected]>
Date: Tue May 24 09:20:51 2016 +0200
i965/vec4: add a scalarization pass for double-precision instructions
The hardware only supports 32-bit swizzles, which means that we can
only access directly channels XY of a DF making access to channels ZW
more difficult, specially considering the various regioning restrictions
imposed by the hardware. The combination of both things makes handling
ramdom swizzles on DF operands rather difficult, as there are many
combinations that can't be represented at all, at least not without
some work and some level of instruction splitting depending on the case.
Writemasks are 64-bit in general, however XY and ZW writemasks also work
in 32-bit, which means these writemasks can't be represented natively,
adding to the complexity.
For now, we decided to try and simplify things as much as possible to
avoid dealing with all this from the get go by adding a scalarization
pass that runs after the main optimization loop. By fully scalarizing
DF instructions in align16 we avoid most of the complexity introduced
by the aforementioned hardware restrictions and we have an easier path
to an initial fully functional version for the vector backend in Haswell
and IvyBridge.
Later, we can improve the implementation so we don't necessarily
scalarize everything, iteratively adding more complexity and building
on top of a framework that is already working. Curro drafted some ideas
for how this could be done here:
https://bugs.freedesktop.org/show_bug.cgi?id=92760#c82
v2:
- Use a copy constructor for the scalar instructions so we copy all
relevant instructions fields from the original instruction.
v3: Fix indention in one switch (Matt)
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f4b8649233fa10e89205b6b5f6f334279b198f22
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Jun 17 08:47:29 2016 +0200
i965/vec4: split double-precision SEL
There is a hardware bug affecting compressed double-precision SEL
instructions in align16 mode by which they won't read predication mask
properly. The bug does not affect other predicated instructions
and it does not affect SEL in Align1 mode either. This was found
empirically and verified by Curro in the simulator.
Fix this by splitting double-precision SEL in Align16 mode to use an
execution size of 4.
v2: Check that the dst type is 64-bit, since we can have 16-wide single
precision bcsel instructions that also write 2 registers.
v3: Replace bcsel by SEL in all the comments as bcsel is the nir opcode
but SEL is the actual assembly instruction (Matt).
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5356d52f31b8285c97f2c920e28cf4eb2a8caa58
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Sep 15 11:30:32 2016 +0200
i965/vec4: teach cmod propagation about different execution sizes
We can't propagate the conditional modifier from one instruction to
another of a different execution size / group, since that would change
the channels affected by the conditional.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f39b3668afbd9569e34a089866d364a78f4db2c
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Jun 16 13:49:55 2016 +0200
i965/vec4: teach CSE about exec_size, group and doubles
v2: adapt to changes in offset()
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca63a3ce5107435197a6272233d66c8831cd3603
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Jun 17 08:21:19 2016 +0200
i965/disasm: print NibCtrl for instructions with execsize < 8
v2 (Curro):
- Print it also for execsize < 4.
- QtrCtrl is still in effect, so print 2 * qtr_ctl + nib_ctl + 1
- Do not read the nib ctl from the instruction in gen < 7,
the field only exists in gen7+.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a83608f50483ac397545d3815bfe8dc3be5126b6
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Jun 29 08:40:27 2016 +0200
i965/vec4: dump NibCtrl for instructions with execsize != 8
v2: do it in the same fashion as the FS backend for consistency (Curro)
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e481dcc35eefdc9d9c8dc97370174405746a36d3
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Jun 17 08:49:44 2016 +0200
i965/vec4: make the generator set correct NibCtrl for SIMD4 DF instructions
From the HSW PRM, Command Reference, QtrCtrl:
"NibCtrl is only allowed for SIMD4 instructions with a DF (Double Float)
source or destination type."
v2: Assert that the type is DF (Samuel)
v3: Don't set the default group to 0 and then set it only for 4-wide
instructions. Instead, assert that exec size and group are always
a correct match and then always set the default group from the
instruction. (Curro)
Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=58767f0fec7809c3408adbc4d147dd56f2ee3d4d
Author: Iago Toral Quiroga <[email protected]>
Date: Mon Aug 29 10:41:45 2016 +0200
i965/vec4: add a SIMD lowering pass
Generally, instructions in Align16 mode only ever write to a single
register and don't need any form of SIMD splitting, that's why we
have never had a SIMD splitting pass in the vec4 backend. However,
double-precision instructions typically write 2 registers and in
some cases they run into certain hardware bugs and limitations
that we need to work around by splitting the instructions so we only
write to 1 register at a time. This patch implements a SIMD splitting
pass similar to the one in the scalar backend.
Because we only use double-precision instructions in Align16 mode
in gen7 (gen8+ is fully scalar and gens < 7 do not implement fp64)
the pass should be a no-op on any other generation.
For now the pass only handles the gen7 restriction where any
instruction that writes 2 registers also needs to read 2 registers.
This affects double-precision instructions reading uniforms, for
example. Later patches will extend the lowering pass adding a few
more cases.
v2:
- Move the simd lowering pass after the main optimization loop and
run copy-propagation and dce if it reports progress (Curro)
- Compute number of registers written instead of fixing it to 1 (Iago)
- Use group from backend_instruction (Iago)
- Drop assertion that checked that we only split 8-wide instructions
into 4-wide. (Curro)
- Don't assume that instructions can only be 8-wide, we might want
to use 16-wide instructions in the future too (Curro)
- Wrap gen7 workarounds in a conditional to ease adding workarounds
for other gens in the future (Curro)
- Handle dst/src overlap hazard (Curro)
- Use the horiz_offset() helper to simplify the implementation (Curro)
- Drop the assertion that checks that each split instruction writes
exactly one register (Curro)
- Use the copy constructor to generate split instructions with all
the relevant fields initialized to the values in the original
instruction instead of copying only a handful of them manually (Curro)
v3 (Iago):
- When copying to a temporary, allocate the number of registers required
for the copy based on the size written of the lowered instruction
instead of assuming that all lowered instructions produce single-register
writes
- Adapt to changes in offset()
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=945269ab7280b772807e573dfefc0b4f967ec522
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Aug 25 12:02:43 2016 +0200
i965: move the group field from fs_inst to backend_instruction.
Just like the exec_size, we are going to need this in the vec4 backend
when we implement a simd splitting pass.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=07cadc306ec161fdf566918175f8d8fc618d9c1b
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Aug 25 10:02:45 2016 +0200
i965/vec4: add a horiz_offset() helper
This will come in handy when we implement a simd lowering pass in a
follow-up patch.
v2: use byte_offset()
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4ea3bf8ebb56c8db6e885a77d81502a0b2adca4f
Author: Juan A. Suarez Romero <[email protected]>
Date: Fri Jun 10 13:55:00 2016 +0200
i965/vec4: handle 32 and 64 bit channels in liveness analysis
Our current data flow analysis does not take into account that channels
on 64-bit operands are 64-bit. This is a problem when the same register
is accessed using both 64-bit and 32-bit channels. This is very common
in operations where we need to access 64-bit data in 32-bit chunks,
such as the double packing and packing operations.
This patch changes the analysis by checking the bits that each source
or destination datatype needs. Actually, rather than bits, we use
blocks of 32bits, which is the minimum channel size.
Because a vgrf can contain a dvec4 (256 bits), we reserve 8
32-bit blocks to map the channels.
v2 (Curro):
- Simplify code by making the var_from_reg helpers take an extra
argument with the register component we want.
- Fix a couple of cases where we had to update the code to the new
way of representing live variables.
v3:
- Fix indent in multiline expressions (Matt)
- Fix comment's closing tag (Matt)
- Use DIV_ROUND_UP(inst->size_written, 16) instead of 2 *
regs_written(inst)
to avoid rounding issues. The same for regs_read(i). (Curro).
- Add asserts in var_from_reg() to avoid exceeding the allocated
registers (Curro).
Reviewed-by: Francisco Jerez <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=29dd5cf9d64ac998cb313db8a908272a6154ec46
Author: Iago Toral Quiroga <[email protected]>
Date: Mon May 30 13:36:30 2016 +0200
i965/vec4: dump the instruction execution size
Reviewed-by: Francisco Jerez <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=486fd5422c09bbd9b951b3b7124f1a904ecff709
Author: Iago Toral Quiroga <[email protected]>
Date: Mon Aug 29 10:45:47 2016 +0200
i965/vec4: use the IR's execution size
In the vec4 backend the generator sets to 8 the execution size for all
instructions by default, however, to implement 64-bit floating-point we
will need to split certain instruction into smaller sizes so we need the
IR to convey this information like we do in the scalar backend. This patch
uses the execution size from the vec4 IR.
We will use this feature in a later patch when we implement a SIMD
splitting pass.
v2:
- Drop the assertion on the execution size being 8 or 4 (Curro)
- Use exec_size from backend_instruction (Curro)
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f79547840a1951dbf82c7b6629935c6e89020e27
Author: Iago Toral Quiroga <[email protected]>
Date: Mon May 30 13:20:31 2016 +0200
i965/vec4: fix regs_read() for doubles
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c6fba5e7cf7af622007c1e5d790152d4fc93ced
Author: Iago Toral Quiroga <[email protected]>
Date: Mon May 30 13:31:25 2016 +0200
i965/vec4: fix size_written for doubles
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9527a50da06f03885aad9e0f6d5693ced6c22bd4
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Aug 25 11:49:53 2016 +0200
i965: move exec_size from fs_instruction to backend_instruction
We are going to need this in the vec4 backend too.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b58026b31e7258a4bd2bb630a1d41a433fb01799
Author: Samuel Iglesias Gonsálvez <[email protected]>
Date: Thu Jul 7 13:35:30 2016 +0200
i965/vec4: use the new helper function to create double immediates
Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=98da3623d5dfd991362c4fd3571325fe0277a2f9
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Mar 9 16:37:33 2016 +0100
i965/vec4: add a helper function to create double immediates
Gen7 hardware does not support double immediates so these need
to be moved in 32-bit chunks to a regular vgrf instead. Instead
of doing this every time we need to create a DF immediate,
create a helper function that does the right thing depending
on the hardware generation.
v2 (Curro):
- Use swizzle() and writemask() helpers and make tmp const.
v3 (Iago):
- Adapt to changes in offset()
Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f9ce5fa22c04b5b34aa6dc67e4a9b2d151d293d
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Feb 18 09:24:16 2016 +0100
i965/vec4: fix optimize predicate for doubles
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1816ae8f68e395da26dcfea2539bafd715c8dbc4
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Feb 5 10:12:57 2016 +0100
i965/vec4: implement fsign() for doubles
v2: use a MOV with a conditional_mod instead of a CMP, like we do in d2b,
to skip
loading a double immediate.
v3: Fix comment (Matt)
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e570619e0755a50b2c8d57c6d1189fb9aca899d
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Feb 17 13:08:47 2016 +0100
i965/vec4: implement d2b
v2 (Curro):
- Generate the flag register with a MOV with conditional_mod instead of a
CMP
instruction, which has the benefit that we can skip loading a DF
0.0 constant.
- Avoid the PICK_LOW_32BIT + MOV by using the flag result and a
SEL to set the boolean result.
v3:
- Fix comment (Matt)
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c1fb525016e41658d2dc5d581da4e83b8a075fd4
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Feb 17 11:12:19 2016 +0100
i965/vec4: implement d2i, d2u, i2d and u2d
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4b2257623494ea8e7a1c7b6fbb2f4f3e59522468
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Jun 29 13:08:25 2016 +0200
i965/vec4: implement HW workaround for align16 double to float conversion
From the BDW PRM, Workarounds chapter:
"DF->f format conversion for Align16 has wrong emask calculation when
source is immediate."
Notice that Broadwell and later are strictly scalar at the moment though, so
this is not really necessary.
v2: Instead of moving the immediate to a vgrf and converting from there,
just
convert the double immediate to float in the compiler and move the
result
to the destination (Matt)
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfc1f0f017db6bd11a558237c9a4ebeacf73f5ba
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Jun 29 13:07:35 2016 +0200
i965/vec4: add helpers for conversions to/from doubles
Use these helpers to implement d2f and f2d. We will reuse these helpers when
we implement things like d2i or i2d as well.
v2:
- Rename the helpers (Matt)
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c722a8e61ebc72d7d21c2bed0f623218d739fdb7
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Feb 17 10:32:05 2016 +0100
i965/vec4: Rename DF to/from F generator opcodes
The opcodes are not specific for conversions to/from float since we need
the same for conversions to/from other 32-bit types. Rename the opcodes
accordingly and change the asserts to check the size of the types involved
instead.
v2:
- Rename to VEC4_OPCODE_TO_DOUBLE and VEC4_OPCODE_FROM_DOUBLE (Matt)
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=619271ec8785ab8b6021d0f49e98c51d457eab4d
Author: Iago Toral Quiroga <[email protected]>
Date: Mon Feb 15 10:07:42 2016 +0100
i965/vec4: fix register allocation for 64-bit undef sources
Reviewed-by: Francisco Jerez <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=21cf6f14d5abdf7d0f9641404387e0c00de6f56f
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Feb 12 13:10:06 2016 +0100
i965/vec4: make opt_vector_float ignore doubles
The pass does not support doubles in its current form.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8318b120e53518ae4d933acd876b8dbd3871e0c
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Feb 12 08:47:21 2016 +0100
i965/vec4: fix get_nir_dest() to use DF type for 64-bit destinations
v2: Make dst_reg_for_nir_reg() handle this for nir_register since we
want to have the correct type set before we call offset().
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb0e67d55dbd353e9c57b0709fa3e534f1aba05f
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Oct 5 10:54:35 2016 +0200
i965/vec4: fix indentation in get_nir_src()
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8cdbbbd2cf9e0c42114c7090805fa2b4a93ca499
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Aug 13 15:34:24 2015 -0700
i965/vec4/nir: implement double comparisons
v2:
- Added newline before if() (Matt)
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a3ba033397bc627e499fcd3a379984ba4d587d2
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Jun 1 09:57:06 2016 +0200
i965/vec4: implement double packing
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=94cfdf586a6a95bd06b989bba27d85f9bf99b9df
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Jun 1 09:58:00 2016 +0200
i965/vec4: implement double unpacking
Reviewed-by: Ian Romanick <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ec57e91d6e4fa8ad4079eef080bd2ab591883e2
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Feb 11 14:19:58 2016 +0100
i965/vec4: don't copy propagate vector opcodes that operate in align1 mode
Basically, ALIGN1 mode will ignore swizzles on the input vectors so we don't
want the copy propagation pass to mess with them.
Reviewed-by: Ian Romanick <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=553700cf55712ae7269ec4225310a2bf0539f64e
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Aug 24 11:21:57 2016 +0200
i965/vec4: Fix DCE for VEC4_OPCODE_SET_{LOW,HIGH}_32BIT
These align1 opcodes do partial writes of 64-bit data. The problem is that
we
want to use them to write on the same register to implement packDouble2x32
and
from the point of view of DCE, since both opcodes write to the same
register,
only the last one stands and decides to eliminate the first, which is
not correct, so prevent this from happening.
v2: Make a helper in vec4_instruction to know if the instruction is an
align1 partial write. This will come in handy when we implement a
simd splitting pass in a later patch.
Reviewed-by: Ian Romanick <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=54b998e0e488189307d2614fe56a3b78b442d316
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Jun 17 12:19:35 2016 +0200
i965/vec4: add VEC4_OPCODE_SET_{LOW,HIGH}_32BIT opcodes
These opcodes will set the low/high 32-bit in each 64-bit data element
using Align1 mode. We will use this to implement packDouble2x32.
We use Align1 mode because in order to implement this in Align16 mode
we would need to use 32-bit logical swizzles (XZ for low, YW for high),
but the IR works in terms of 64-bit logical swizzles for DF operands
all the way up to codegen.
v2:
- use suboffset() instead of get_element_ud()
- no need to set the width on the dst
Reviewed-by: Ian Romanick <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6979e5a41241993b9e7bedea80f29fb43d96aa47
Author: Iago Toral Quiroga <[email protected]>
Date: Tue May 31 10:17:37 2016 +0200
i965/vec4: add VEC4_OPCODE_PICK_{LOW,HIGH}_32BIT opcodes
These opcodes will pick the low/high 32-bit in each 64-bit data element
using Align1 mode. We will use this, for example, to do things like
unpackDouble2x32.
We use Align1 mode because in order to implement this in Align16 mode
we would need to use 32-bit logical swizzles (XZ for low, YW for high),
but the IR works in terms of 64-bit logical swizzles for DF operands
all the way up to codegen.
v2:
- use suboffset() instead of get_element_ud()
- no need to set the width on the dst
Reviewed-by: Ian Romanick <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b6174dffa4c085a0b7f66db6c46b831c5c91f0b
Author: Iago Toral Quiroga <[email protected]>
Date: Fri Feb 5 10:11:48 2016 +0100
i965/vec4: add dst_null_df()
Reviewed-by: Francisco Jerez <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c040332f56ca2e5a4bbd8c412fd32ab3ff821db
Author: Iago Toral Quiroga <[email protected]>
Date: Tue Nov 10 10:20:25 2015 +0100
i965/vec4: We only support 32-bit integer ALU operations for now
Add asserts so we remember to address this when we enable 64-bit
integer support, as suggested by Connor and Jason.
Reviewed-by: Francisco Jerez <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=611fe6b32fae09b3ae52afd4bdb7bae29eca99df
Author: Iago Toral Quiroga <[email protected]>
Date: Wed May 25 08:21:23 2016 +0200
i965/disasm: align16 DF source regions have a width of 2
Reviewed-by: Francisco Jerez <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c35fa7ac5507a64943aa518b2dac8bddfdc9e14b
Author: Iago Toral Quiroga <[email protected]>
Date: Wed Nov 18 14:00:58 2015 +0100
i965/vec4: set correct register regions for 32-bit and 64-bit
For 32-bit instructions we want to use <4,4,1> regions for VGRF
sources so we should really set a width of 4 (we were setting 8).
For 64-bit instructions we want to use a width of 2 because the
hardware uses 32-bit swizzles, meaning that we can only address 2
consecutive 64-bit components in a row. Also, Curro suggested that
the hardware is probably fixing the width to 2 for 64-bit instructions
anyway, so just go with that and use <2,2,1>.
v2:
- No need to explicitly set the vertical stride of 64-bit regions to 2,
brw_vecn_grf with a width of 2 will do that for us.
- No need to adjust the width of dst registers.
v3 (Ian):
- Make type_size and width const.
Signed-off-by: Connor Abbott <[email protected]>
Reviewed-by: Ian Romanick <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed74b19ab49f9c47ffe40309fee201697c347c3e
Author: Connor Abbott <[email protected]>
Date: Thu Aug 13 14:22:03 2015 -0700
i965: add brw_vecn_grf()
Reviewed-by: Francisco Jerez <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e09a6be3b6806c582347f6faf93cc2d824d98ed2
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Aug 13 15:56:22 2015 -0700
i965/vec4: translate d2f/f2d
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=558f27953101c438747c3e9d3c3f98ce21e79007
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Aug 13 15:36:05 2015 -0700
i965/vec4: add double/float conversion pseudo-opcodes
These need to be emitted as align1 MOV's, since they need to have a
stride of 2 on the float register (whether src or dest) so that data
from another thread doesn't cross the middle of a SIMD8 register.
v2 (Iago):
- The float-to-double needs to align 32-bit data to 64-bit before doing the
conversion. This was doable in align16 when we tried to use an execsize
of 4, but with an execsize of 8 we would need another align1 opcode to do
that (since we need data to cross the middle of a SIMD register). Just
making the opcode handle this internally seems more practical that adding
another opcode just for this purpose and having the caller know about this
before converting.
- The double-to-float conversion produces 32-bit elements aligned to 64-bit
so we make the opcode re-pack the result to 32-bit and fit in one register,
as expected by SIMD4x2 operation. This still requires that callers reserve
two registers for the float data destination because we need to produce
64-bit aligned data first, and repack it later on the same destination
register, but it saves the need for a re-pack opcode only to achieve this
making the operation complete in a single opcode. Hopefully that is worth
the weirdness of the double register allocation...
Signed-off-by: Connor Abbott <[email protected]>
Signed-off-by: Iago Toral Quiroga <[email protected]>
Reviewed-by: Ian Romanick <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d6eee3144ce16b39909522be466bdb3871f4c1b
Author: Connor Abbott <[email protected]>
Date: Thu Aug 13 14:18:04 2015 -0700
i965/vec4: add support for printing DF immediates
Reviewed-by: Francisco Jerez <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ce4b20bde4f4ca8e8907fcac13e8bb9d7e5f4b4
Author: Iago Toral Quiroga <[email protected]>
Date: Thu Aug 13 15:30:34 2015 -0700
i965/vec4/nir: fix emitting 64-bit immediates
Reviewed-by: Ian Romanick <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3457252b74f5490cff8915cac1e5fe0bf1031f5b
Author: Connor Abbott <[email protected]>
Date: Thu Aug 13 14:35:46 2015 -0700
i965/vec4/nir: set the right type for 64-bit registers
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fef06f635610ddc730a213576e59afb638c6051d
Author: Iago Toral Quiroga <[email protected]>
Date: Wed May 25 09:27:49 2016 +0200
i965/vec4/nir: support doubles in ALU operations
Basically, this involves considering the bit-size information to set
the appropriate type on both operands and destination.
v2 (Curro)
- Don't use two temporaries (and write one of them twice ) to obtain
the nir_alu_type.
Reviewed-by: Francisco Jerez <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f096b1e5a5e31a5efba7279326ec8bc8478bb56
Author: Iago Toral Quiroga <[email protected]>
Date: Mon Nov 2 00:07:27 2015 -0500
i965/vec4/nir: Add bit-size information to types
Reviewed-by: Francisco Jerez <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d81a292036445c440e56d07ce3d5294e0411d71
Author: Connor Abbott <[email protected]>
Date: Mon Feb 29 12:35:05 2016 +0100
i965/vec4/nir: allocate two registers for dvec3/dvec4
v2 (Curro):
- Do not special-case for a bit-size of 64, divide the bit_size by 32
instead.
- Use DIV_ROUND_UP so we can handle sub-32-bit types.
v3 (Ian):
- Make num_regs const.
Reviewed-by: Ian Romanick <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=54913850aa379f57fcbf7a2dec5ea236cf997646
Author: Connor Abbott <[email protected]>
Date: Mon Aug 10 11:35:34 2015 -0700
i965/vec4/nir: simplify glsl_type_for_nir_alu_type()
Less duplication, one one less case to handle for doubles and support
for sized NIR types.
v2: Fix call to get_instance by swapping rows and columns params (Iago)
Signed-off-by: Iago Toral Quiroga <[email protected]>
Reviewed-by: Francisco Jerez <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9fa24632f3852eb3c506708912ab4257ea6b8ed1
Author: Samuel Iglesias Gonsálvez <[email protected]>
Date: Mon Jun 6 15:49:52 2016 +0200
i965/nir: double/dvec2 uniforms only need to be padded to a single vec4 slot
max_vector_size is used in the vec4 backend to pad out the uniform
components to match a size that is a multiple of a vec4. Double and dvec2
uniforms only require a single vec4 slot, not two.
Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]>
Signed-off-by: Iago Toral Quiroga <[email protected]>
Reviewed-by: Timothy Arceri <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
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