Module: Mesa Branch: master Commit: 5eeebca12f1c10aecf7eba3ca15744145e6f921e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5eeebca12f1c10aecf7eba3ca15744145e6f921e
Author: Ilia Mirkin <[email protected]> Date: Mon Jan 16 14:25:15 2017 -0500 nv50/ir: handle new DDIV op which will be used for double divisions The existing lowering is in place to lower that to RCP + MUL, or fancier things down the line if necessary. Signed-off-by: Ilia Mirkin <[email protected]> --- src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp index 86348e7..6b38d5f 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp @@ -612,6 +612,7 @@ nv50_ir::DataType Instruction::inferSrcType() const case TGSI_OPCODE_DNEG: case TGSI_OPCODE_DADD: case TGSI_OPCODE_DMUL: + case TGSI_OPCODE_DDIV: case TGSI_OPCODE_DMAX: case TGSI_OPCODE_DMIN: case TGSI_OPCODE_DSLT: @@ -810,6 +811,7 @@ static nv50_ir::operation translateOpcode(uint opcode) NV50_IR_OPCODE_CASE(DNEG, NEG); NV50_IR_OPCODE_CASE(DADD, ADD); NV50_IR_OPCODE_CASE(DMUL, MUL); + NV50_IR_OPCODE_CASE(DDIV, DIV); NV50_IR_OPCODE_CASE(DMAX, MAX); NV50_IR_OPCODE_CASE(DMIN, MIN); NV50_IR_OPCODE_CASE(DSLT, SET); @@ -3745,6 +3747,7 @@ Converter::handleInstruction(const struct tgsi_full_instruction *insn) } case TGSI_OPCODE_DADD: case TGSI_OPCODE_DMUL: + case TGSI_OPCODE_DDIV: case TGSI_OPCODE_DMAX: case TGSI_OPCODE_DMIN: FOR_EACH_DST_ENABLED_CHANNEL(0, c, tgsi) { _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
