Module: Mesa Branch: master Commit: 0ae1f4a5eaa77d6f26771997d8c55a2730df660c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ae1f4a5eaa77d6f26771997d8c55a2730df660c
Author: Matt Turner <[email protected]> Date: Tue Nov 22 10:40:08 2016 -0800 i965: Split gen_device_info_i965 between brw and cl. cl (Crestline) supports a few more things than brw (Broadwater). Sort and sync PCI IDs from the kernel. The G45 PRMs use the following code names PRM Codename Marketing DevBW Broadwater GMA X3000 DevCL Crestline GMA X3100 DevBW-E Bearlake GMA X3500 DevBW-E seems to just be the "E stepping" of Broadwater, with some software-visible fixes that we've never implemented. https://en.wikipedia.org/wiki/List_of_Intel_chipsets --- include/pci_ids/i965_pci_ids.h | 12 ++++++------ src/intel/common/gen_device_info.c | 27 ++++++++++++++++---------- src/mesa/drivers/dri/i965/test_eu_validate.cpp | 4 +++- 3 files changed, 26 insertions(+), 17 deletions(-) diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index ffcaf33..0c6ae21 100644 --- a/include/pci_ids/i965_pci_ids.h +++ b/include/pci_ids/i965_pci_ids.h @@ -1,9 +1,9 @@ -CHIPSET(0x29A2, i965, "Intel(R) 965G") -CHIPSET(0x2992, i965, "Intel(R) 965Q") -CHIPSET(0x2982, i965, "Intel(R) 965G") -CHIPSET(0x2972, i965, "Intel(R) 946GZ") -CHIPSET(0x2A02, i965, "Intel(R) 965GM") -CHIPSET(0x2A12, i965, "Intel(R) 965GME/GLE") +CHIPSET(0x2972, brw, "Intel(R) 946GZ (Broadwater)") +CHIPSET(0x2982, brw, "Intel(R) G35 (Bearlake)") +CHIPSET(0x2992, brw, "Intel(R) 965Q (Broadwater)") +CHIPSET(0x29A2, brw, "Intel(R) 965G (Broadwater)") +CHIPSET(0x2A02, cl, "Intel(R) 965GM (Crestline)") +CHIPSET(0x2A12, cl, "Intel(R) 965GME/GLE (Crestline)") CHIPSET(0x2A42, g4x, "Mobile Intel® GM45 Express Chipset") CHIPSET(0x2E02, g4x, "Intel(R) Integrated Graphics Device") CHIPSET(0x2E12, g4x, "Intel(R) Q45/Q43") diff --git a/src/intel/common/gen_device_info.c b/src/intel/common/gen_device_info.c index 9bf3cd5..b6f2069 100644 --- a/src/intel/common/gen_device_info.c +++ b/src/intel/common/gen_device_info.c @@ -26,16 +26,23 @@ #include "gen_device_info.h" #include "compiler/shader_enums.h" -static const struct gen_device_info gen_device_info_i965 = { - .gen = 4, - .has_negative_rhw_bug = true, - .num_slices = 1, - .max_vs_threads = 16, - .max_gs_threads = 2, - .max_wm_threads = 8 * 4, - .urb = { - .size = 256, - }, +#define GEN4_FEATURES \ + .gen = 4, \ + .has_negative_rhw_bug = true, \ + .num_slices = 1, \ + .max_vs_threads = 16, \ + .max_gs_threads = 2, \ + .max_wm_threads = 8 * 4, \ + .urb = { \ + .size = 256, \ + } \ + +static const struct gen_device_info gen_device_info_brw = { + GEN4_FEATURES, +}; + +static const struct gen_device_info gen_device_info_cl = { + GEN4_FEATURES, }; static const struct gen_device_info gen_device_info_g4x = { diff --git a/src/mesa/drivers/dri/i965/test_eu_validate.cpp b/src/mesa/drivers/dri/i965/test_eu_validate.cpp index 76652dc..16f871b 100644 --- a/src/mesa/drivers/dri/i965/test_eu_validate.cpp +++ b/src/mesa/drivers/dri/i965/test_eu_validate.cpp @@ -26,7 +26,8 @@ #include "util/ralloc.h" enum subgen { - IS_G45 = 1, + IS_CL = 1, + IS_G45, IS_BYT, IS_HSW, IS_CHV, @@ -40,6 +41,7 @@ static const struct gen_info { enum subgen subgen; } gens[] = { { "brw", 4 }, + { "cl", 4, IS_CL }, { "g45", 4, IS_G45 }, { "ilk", 5 }, { "snb", 6 }, _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
