Module: Mesa
Branch: master
Commit: f938354362655a378d474c5f79c52cea9852ab91
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f938354362655a378d474c5f79c52cea9852ab91
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Mar 31 15:23:35 2017 -0700
i965/blorp: Align vertex buffers to 64B
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Cc: "13.0 17.0" <mesa-sta...@lists.freedesktop.org>
---
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
index f9334ee13d..b7a23afab4 100644
--- a/src/mesa/drivers/dri/i965/genX_blorp_exec.c
+++ b/src/mesa/drivers/dri/i965/genX_blorp_exec.c
@@ -122,8 +122,20 @@ blorp_alloc_vertex_buffer(struct blorp_batch *batch,
uint32_t size,
assert(batch->blorp->driver_ctx == batch->driver_batch);
struct brw_context *brw = batch->driver_batch;
+ /* From the Skylake PRM, 3DSTATE_VERTEX_BUFFERS:
+ *
+ * "The VF cache needs to be invalidated before binding and then using
+ * Vertex Buffers that overlap with any previously bound Vertex Buffer
+ * (at a 64B granularity) since the last invalidation. A VF cache
+ * invalidate is performed by setting the "VF Cache Invalidation Enable"
+ * bit in PIPE_CONTROL."
+ *
+ * This restriction first appears in the Skylake PRM but the internal docs
+ * also list it as being an issue on Broadwell. In order to avoid this
+ * problem, we align all vertex buffer allocations to 64 bytes.
+ */
uint32_t offset;
- void *data = brw_state_batch(brw, size, 32, &offset);
+ void *data = brw_state_batch(brw, size, 64, &offset);
*addr = (struct blorp_address) {
.buffer = brw->batch.bo,
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