Module: Mesa Branch: master Commit: 797890bbbd3b4d5415005af782244b255cb9c488 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=797890bbbd3b4d5415005af782244b255cb9c488
Author: Lucas Stach <[email protected]> Date: Mon Nov 21 12:29:04 2016 +0100 etnaviv: enable TS also on sampler resources Fixes a performance issue with imported winsys buffers as those are marked with binding sampler view. This might require a TS flush on single pipe chips that directly sample from the rendered buffer, but otherwise seems to work fine. Signed-off-by: Lucas Stach <[email protected]> Reviewed-by: Wladimir J. van der Laan <[email protected]> --- src/gallium/drivers/etnaviv/etnaviv_surface.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/gallium/drivers/etnaviv/etnaviv_surface.c b/src/gallium/drivers/etnaviv/etnaviv_surface.c index db4846aa06..7ac2862e12 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_surface.c +++ b/src/gallium/drivers/etnaviv/etnaviv_surface.c @@ -64,12 +64,9 @@ etna_create_surface(struct pipe_context *pctx, struct pipe_resource *prsc, * indicate the tile status module bypasses the memory * offset and MMU. */ - /* XXX for now, don't do TS for render textures as this path - * is not stable. */ if (VIV_FEATURE(ctx->screen, chipFeatures, FAST_CLEAR) && VIV_FEATURE(ctx->screen, chipMinorFeatures0, MC20) && !DBG_ENABLED(ETNA_DBG_NO_TS) && !rsc->ts_bo && - !(rsc->base.bind & (PIPE_BIND_SAMPLER_VIEW)) && (rsc->levels[level].padded_width & ETNA_RS_WIDTH_MASK) == 0 && (rsc->levels[level].padded_height & ETNA_RS_HEIGHT_MASK) == 0) { etna_screen_resource_alloc_ts(pctx->screen, rsc); _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
