Module: Mesa Branch: master Commit: ebc7011ab0349e8c193b8c3db18d9064748dfd1a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ebc7011ab0349e8c193b8c3db18d9064748dfd1a
Author: Kenneth Graunke <[email protected]> Date: Tue Apr 11 08:33:20 2017 -0700 i965: Set kernel features before computing max GL version. We check these bitfields when computing the Haswell max GL version. We need to set them ahead of time, or they won't exist, and all our checks will fail. That sets the max core profile GL version to 4.2. This introduces the bizarre situation where asking for a GL context with version 4.3+ fails, but asking for a GL core profile context with version <= 4.2 actually promotes you a 4.5 context. GLX_MESA_query_renderer also reported the bogus 4.2 value. Now it shows 4.5. Reported-and-tested-by: Rafael Ristovski <[email protected]> --- src/mesa/drivers/dri/i965/intel_screen.c | 48 ++++++++++++++++---------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 96e7a39863..76e82b03b2 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -2005,6 +2005,30 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) screen->kernel_features |= KERNEL_ALLOWS_SOL_OFFSET_WRITES; } + if (devinfo->gen >= 8 || screen->cmd_parser_version >= 2) + screen->kernel_features |= KERNEL_ALLOWS_PREDICATE_WRITES; + + /* Haswell requires command parser version 4 in order to have L3 + * atomic scratch1 and chicken3 bits + */ + if (devinfo->is_haswell && screen->cmd_parser_version >= 4) { + screen->kernel_features |= + KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3; + } + + /* Haswell requires command parser version 6 in order to write to the + * MI_MATH GPR registers, and version 7 in order to use + * MI_LOAD_REGISTER_REG (which all users of MI_MATH use). + */ + if (devinfo->gen >= 8 || + (devinfo->is_haswell && screen->cmd_parser_version >= 7)) { + screen->kernel_features |= KERNEL_ALLOWS_MI_MATH_AND_LRR; + } + + /* Gen7 needs at least command parser version 5 to support compute */ + if (devinfo->gen >= 8 || screen->cmd_parser_version >= 5) + screen->kernel_features |= KERNEL_ALLOWS_COMPUTE_DISPATCH; + const char *force_msaa = getenv("INTEL_FORCE_MSAA"); if (force_msaa) { screen->winsys_msaa_samples_override = @@ -2036,30 +2060,6 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen) (ret != -1 || errno != EINVAL); } - if (devinfo->gen >= 8 || screen->cmd_parser_version >= 2) - screen->kernel_features |= KERNEL_ALLOWS_PREDICATE_WRITES; - - /* Haswell requires command parser version 4 in order to have L3 - * atomic scratch1 and chicken3 bits - */ - if (devinfo->is_haswell && screen->cmd_parser_version >= 4) { - screen->kernel_features |= - KERNEL_ALLOWS_HSW_SCRATCH1_AND_ROW_CHICKEN3; - } - - /* Haswell requires command parser version 6 in order to write to the - * MI_MATH GPR registers, and version 7 in order to use - * MI_LOAD_REGISTER_REG (which all users of MI_MATH use). - */ - if (devinfo->gen >= 8 || - (devinfo->is_haswell && screen->cmd_parser_version >= 7)) { - screen->kernel_features |= KERNEL_ALLOWS_MI_MATH_AND_LRR; - } - - /* Gen7 needs at least command parser version 5 to support compute */ - if (devinfo->gen >= 8 || screen->cmd_parser_version >= 5) - screen->kernel_features |= KERNEL_ALLOWS_COMPUTE_DISPATCH; - dri_screen->extensions = !screen->has_context_reset_notification ? screenExtensions : intelRobustScreenExtensions; _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
