Module: Mesa Branch: 17.1 Commit: ae55ab84b5e2faf35e42bf8ab03cbcc69f3fef04 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae55ab84b5e2faf35e42bf8ab03cbcc69f3fef04
Author: Jason Ekstrand <[email protected]> Date: Wed May 17 11:54:24 2017 -0700 anv: Require vertex buffers to come from a 32-bit heap Reviewed-by: Nanley Chery <[email protected]> Cc: "17.1" <[email protected]> (cherry picked from commit 39adea9330376a64a4b5e8da98f5e055ebd3331e) Signed-off-by: Juan A. Suarez Romero <[email protected]> --- src/intel/vulkan/anv_device.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 726ccce085..5bfbf84d31 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -153,6 +153,18 @@ anv_physical_device_init_heaps(struct anv_physical_device *device, int fd) for (uint32_t heap = 0; heap < device->memory.heap_count; heap++) { uint32_t valid_buffer_usage = ~0; + /* There appears to be a hardware issue in the VF cache where it only + * considers the bottom 32 bits of memory addresses. If you happen to + * have two vertex buffers which get placed exactly 4 GiB apart and use + * them in back-to-back draw calls, you can get collisions. In order to + * solve this problem, we require vertex and index buffers be bound to + * memory allocated out of the 32-bit heap. + */ + if (device->memory.heaps[heap].supports_48bit_addresses) { + valid_buffer_usage &= ~(VK_BUFFER_USAGE_INDEX_BUFFER_BIT | + VK_BUFFER_USAGE_VERTEX_BUFFER_BIT); + } + if (device->info.has_llc) { /* Big core GPUs share LLC with the CPU and thus one memory type can be * both cached and coherent at the same time. _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
