Module: Mesa Branch: master Commit: 2a5e4f15efb7be113cbc310bb7d809578153953d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a5e4f15efb7be113cbc310bb7d809578153953d
Author: Kenneth Graunke <[email protected]> Date: Mon Jan 25 15:23:24 2016 -0800 i965: Require a UBO offset alignment of 32 bytes. Soon, we're going to start providing UBO data to shaders as push constants, rather than requiring them to issue pull loads. The 3DSTATE_CONSTANT_* commands require 32 byte aligned pointers. So, we need to increase this from 16 to 32. Reviewed-by: Matt Turner <[email protected]> --- src/mesa/drivers/dri/i965/brw_context.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index d8f187ff7e..b23e811f30 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -614,8 +614,11 @@ brw_initialize_context_constants(struct brw_context *brw) * the element in the buffer." * * However, unaligned accesses are slower, so enforce buffer alignment. + * + * In order to push UBO data, 3DSTATE_CONSTANT_XS imposes an additional + * restriction: the start of the buffer needs to be 32B aligned. */ - ctx->Const.UniformBufferOffsetAlignment = 16; + ctx->Const.UniformBufferOffsetAlignment = 32; /* ShaderStorageBufferOffsetAlignment should be a cacheline (64 bytes) so * that we can safely have the CPU and GPU writing the same SSBO on _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
