Module: Mesa Branch: master Commit: b86f86f55cef4672f23cb50871c8cec03deecbd6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b86f86f55cef4672f23cb50871c8cec03deecbd6
Author: Dave Airlie <[email protected]> Date: Tue Jul 11 03:02:09 2017 +0100 radv: allow clear merging for depth/stencil with no care stencil Some of the Sascha Willems demos pick a D32/S8 format for the depth buffer, then do a LOAD_OP_CLEAR/LOAD_OP_DONT_CARE on it, which means we don't get to merge the undefined->depth and clear htile transitions. This add the stencil aspect to the pending clears if there is a depth clear pending and the stencil aspect is don't care. Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Dave Airlie <[email protected]> --- src/amd/vulkan/radv_cmd_buffer.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index a2578126c5..9c20bb003c 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1824,6 +1824,9 @@ radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer, if ((att_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) && att->load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) { clear_aspects |= VK_IMAGE_ASPECT_DEPTH_BIT; + if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && + att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_DONT_CARE) + clear_aspects |= VK_IMAGE_ASPECT_STENCIL_BIT; } if ((att_aspects & VK_IMAGE_ASPECT_STENCIL_BIT) && att->stencil_load_op == VK_ATTACHMENT_LOAD_OP_CLEAR) { _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
