Module: Mesa
Branch: master
Commit: 1e696b962b7207bb87cf9fc91e2a9de9a3becfba
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e696b962b7207bb87cf9fc91e2a9de9a3becfba

Author: Dave Airlie <airl...@redhat.com>
Date:   Fri Aug  4 06:54:15 2017 +0100

radv: add separate fmask tile swizzle counter.

This mirrors what Marek has done for radeonsi, and uses
a separate counter to handle the fmask surface for MSAA
MRTs.

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_device.c  | 2 +-
 src/amd/vulkan/radv_image.c   | 5 ++++-
 src/amd/vulkan/radv_private.h | 7 ++++++-
 3 files changed, 11 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index ce65ba378e..e5bedf32b1 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3042,7 +3042,7 @@ radv_initialise_color_surface(struct radv_device *device,
                va = device->ws->buffer_get_va(iview->bo) + 
iview->image->offset + iview->image->fmask.offset;
                cb->cb_color_fmask = va >> 8;
                if (device->physical_device->rad_info.chip_class < GFX9)
-                       cb->cb_color_fmask |= 
iview->image->surface.tile_swizzle;
+                       cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
        } else {
                cb->cb_color_fmask = cb->cb_color_base;
        }
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index c27c3b6ddc..1ccd4a463f 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -484,7 +484,7 @@ si_make_texture_descriptor(struct radv_device *device,
 
                fmask_state[0] = va >> 8;
                if (device->physical_device->rad_info.chip_class < GFX9)
-                       fmask_state[0] |= image->surface.tile_swizzle;
+                       fmask_state[0] |= image->fmask.tile_swizzle;
                fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
                        S_008F14_DATA_FORMAT_GFX6(fmask_format) |
                        S_008F14_NUM_FORMAT_GFX6(num_format);
@@ -616,6 +616,8 @@ radv_image_get_fmask_info(struct radv_device *device,
        info.samples = 1;
        fmask.flags = image->surface.flags | RADEON_SURF_FMASK;
 
+       info.surf_index = &device->fmask_mrt_offset_counter;
+
        /* Force 2D tiling if it wasn't set. This may occur when creating
         * FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
         * destination buffer must have an FMASK too. */
@@ -644,6 +646,7 @@ radv_image_get_fmask_info(struct radv_device *device,
        out->tile_mode_index = fmask.u.legacy.tiling_index[0];
        out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
        out->bank_height = fmask.u.legacy.bankh;
+       out->tile_swizzle = fmask.tile_swizzle;
        out->alignment = MAX2(256, fmask.surf_alignment);
        out->size = fmask.surf_size;
 }
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 1f0e0252bf..6c49395d0a 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -547,8 +547,12 @@ struct radv_device {
        /* Backup in-memory cache to be used if the app doesn't provide one */
        struct radv_pipeline_cache *                mem_cache;
 
+       /*
+        * use different counters so MSAA MRTs get consecutive surface indices,
+        * even if MASK is allocated in between.
+        */
        uint32_t image_mrt_offset_counter;
-
+       uint32_t fmask_mrt_offset_counter;
        struct list_head shader_slabs;
        mtx_t shader_slab_mutex;
 };
@@ -1193,6 +1197,7 @@ struct radv_fmask_info {
        unsigned bank_height;
        unsigned slice_tile_max;
        unsigned tile_mode_index;
+       unsigned tile_swizzle;
 };
 
 struct radv_cmask_info {

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