Module: Mesa Branch: master Commit: ab6f874439943837c06d3346385f75145e6d2775 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ab6f874439943837c06d3346385f75145e6d2775
Author: Iago Toral Quiroga <[email protected]> Date: Thu Sep 7 12:56:27 2017 +0200 i965: do not fallback to linear tiling for stencil surfaces We were skipping this fallback for depth, but not for stencil which the hardware always requires to be W-tiled. Also, make the checks for whether we need to apply retiling strategies based on usage instead of tiling flags, which is safer and more explicit. This fixes a regression in a CTS test introduced with commit 4ea63fab77f0 that started applying re-tiling stencil surfaces in certain scenarios. v2: discard retiling based on usage fields instead of tiling flags. This is safer and more explicit. v3: Add a comment indicating that texturing of stencil in gen7 requires an Y-tiled copy (Topi). Fixes: KHR-GL45.direct_state_access.renderbuffers_storage Reviewed-by: Topi Pohjolainen <[email protected]> --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 79afdc5342..32394ca3aa 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -570,11 +570,14 @@ make_surface(struct brw_context *brw, GLenum target, mesa_format format, if (!isl_surf_init_s(&brw->isl_dev, &mt->surf, &init_info)) goto fail; - /* In case caller doesn't specifically request Y-tiling (needed - * unconditionally for depth), check for corner cases needing special - * treatment. + /* Depth surfaces are always Y-tiled and stencil is always W-tiled, although + * on gen7 platforms we also need to create Y-tiled copies of stencil for + * texturing since the hardware can't sample from W-tiled surfaces. For + * everything else, check for corner cases needing special treatment. */ - if (tiling_flags & ~ISL_TILING_Y0_BIT) { + bool is_depth_stencil = + mt->surf.usage & (ISL_SURF_USAGE_STENCIL_BIT | ISL_SURF_USAGE_DEPTH_BIT); + if (!is_depth_stencil) { if (need_to_retile_as_linear(brw, mt->surf.row_pitch, mt->surf.tiling, mt->surf.samples)) { init_info.tiling_flags = 1u << ISL_TILING_LINEAR; _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
