Module: Mesa Branch: master Commit: 7bbcb6ac6cf3e09da4387bf9c658c3aa1270db9a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7bbcb6ac6cf3e09da4387bf9c658c3aa1270db9a
Author: Nicolai Hähnle <[email protected]> Date: Tue Sep 26 17:57:59 2017 +0200 radeonsi: move current_rast_prim into si_context v2: rebase fixes Reviewed-by: Marek Olšák <[email protected]> --- src/gallium/drivers/radeon/r600_pipe_common.c | 4 ---- src/gallium/drivers/radeon/r600_pipe_common.h | 1 - src/gallium/drivers/radeonsi/si_pipe.h | 1 + src/gallium/drivers/radeonsi/si_state_draw.c | 10 +++++----- src/gallium/drivers/radeonsi/si_state_shaders.c | 8 ++++---- src/gallium/drivers/radeonsi/si_state_viewport.c | 2 +- 6 files changed, 11 insertions(+), 15 deletions(-) diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c index d50982b863..1aceb5b755 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.c +++ b/src/gallium/drivers/radeon/r600_pipe_common.c @@ -724,10 +724,6 @@ bool si_common_context_init(struct r600_common_context *rctx, rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback; rctx->b.buffer_subdata = si_buffer_subdata; - /* Set a reasonable default to avoid a performance regression in r600 - * on stable branches. */ - rctx->current_rast_prim = PIPE_PRIM_TRIANGLES; - if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) { rctx->b.get_device_reset_status = r600_get_reset_status; rctx->gpu_reset_counter = diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h index 1558943bfe..597ff0280e 100644 --- a/src/gallium/drivers/radeon/r600_pipe_common.h +++ b/src/gallium/drivers/radeon/r600_pipe_common.h @@ -571,7 +571,6 @@ struct r600_common_context { /* Additional context states. */ unsigned flags; /* flush flags */ - enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */ /* Queries. */ /* Maintain the list of active queries for pausing between IBs. */ diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h index b3d5b18645..e0759eddb2 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.h +++ b/src/gallium/drivers/radeonsi/si_pipe.h @@ -433,6 +433,7 @@ struct si_context { unsigned last_sc_line_stipple; unsigned current_vs_state; unsigned last_vs_state; + enum pipe_prim_type current_rast_prim; /* primitive type after TES, GS */ /* Scratch buffer */ struct r600_atom scratch_state; diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 9a6c9c8f84..2d4c9c5b9f 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -531,7 +531,7 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx, static void si_emit_rasterizer_prim_state(struct si_context *sctx) { struct radeon_winsys_cs *cs = sctx->b.gfx.cs; - enum pipe_prim_type rast_prim = sctx->b.current_rast_prim; + enum pipe_prim_type rast_prim = sctx->current_rast_prim; struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer; /* Skip this if not rendering lines. */ @@ -581,7 +581,7 @@ static void si_emit_draw_registers(struct si_context *sctx, { struct radeon_winsys_cs *cs = sctx->b.gfx.cs; unsigned prim = si_conv_pipe_prim(info->mode); - unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->b.current_rast_prim); + unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim); unsigned ia_multi_vgt_param; ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches); @@ -1257,15 +1257,15 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info) } else rast_prim = info->mode; - if (rast_prim != sctx->b.current_rast_prim) { - bool old_is_poly = sctx->b.current_rast_prim >= PIPE_PRIM_TRIANGLES; + if (rast_prim != sctx->current_rast_prim) { + bool old_is_poly = sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES; bool new_is_poly = rast_prim >= PIPE_PRIM_TRIANGLES; if (old_is_poly != new_is_poly) { sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1; si_mark_atom_dirty(sctx, &sctx->scissors.atom); } - sctx->b.current_rast_prim = rast_prim; + sctx->current_rast_prim = rast_prim; sctx->do_update_shaders = true; } diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 42814d9fd5..7619e2f04a 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -1408,10 +1408,10 @@ static inline void si_shader_selector_key(struct pipe_context *ctx, } if (rs) { - bool is_poly = (sctx->b.current_rast_prim >= PIPE_PRIM_TRIANGLES && - sctx->b.current_rast_prim <= PIPE_PRIM_POLYGON) || - sctx->b.current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY; - bool is_line = !is_poly && sctx->b.current_rast_prim != PIPE_PRIM_POINTS; + bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES && + sctx->current_rast_prim <= PIPE_PRIM_POLYGON) || + sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY; + bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS; key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read; key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read; diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c b/src/gallium/drivers/radeonsi/si_state_viewport.c index d462f7d0a2..eb4c00a24d 100644 --- a/src/gallium/drivers/radeonsi/si_state_viewport.c +++ b/src/gallium/drivers/radeonsi/si_state_viewport.c @@ -186,7 +186,7 @@ static void si_emit_guardband(struct si_context *ctx, discard_x = 1.0; discard_y = 1.0; - if (ctx->b.current_rast_prim < PIPE_PRIM_TRIANGLES) { + if (ctx->current_rast_prim < PIPE_PRIM_TRIANGLES) { /* When rendering wide points or lines, we need to be more * conservative about when to discard them entirely. Since * point size can be determined by the VS output, we basically _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
