Module: Mesa
Branch: master
Commit: 7664aaf331220f39bf306b4c8afd62966df1391a
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7664aaf331220f39bf306b4c8afd62966df1391a

Author: Timothy Arceri <[email protected]>
Date:   Wed Oct 11 11:59:20 2017 +1100

radv: remove duplicate debug_flags field

Reviewed-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>

---

 src/amd/vulkan/radv_cmd_buffer.c     | 2 +-
 src/amd/vulkan/radv_debug.c          | 2 +-
 src/amd/vulkan/radv_device.c         | 4 +---
 src/amd/vulkan/radv_image.c          | 4 ++--
 src/amd/vulkan/radv_meta_clear.c     | 4 ++--
 src/amd/vulkan/radv_pipeline.c       | 4 ++--
 src/amd/vulkan/radv_pipeline_cache.c | 2 +-
 src/amd/vulkan/radv_private.h        | 1 -
 src/amd/vulkan/radv_shader.c         | 8 ++++----
 9 files changed, 14 insertions(+), 17 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 67e038a152..495fd67dbb 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -373,7 +373,7 @@ void radv_cmd_buffer_trace_emit(struct radv_cmd_buffer 
*cmd_buffer)
 static void
 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer)
 {
-       if (cmd_buffer->device->debug_flags & RADV_DEBUG_SYNC_SHADERS) {
+       if (cmd_buffer->device->instance->debug_flags & 
RADV_DEBUG_SYNC_SHADERS) {
                enum radv_cmd_flush_bits flags;
 
                /* Force wait for graphics/compute engines to be idle. */
diff --git a/src/amd/vulkan/radv_debug.c b/src/amd/vulkan/radv_debug.c
index cb9509117e..b69c05b64f 100644
--- a/src/amd/vulkan/radv_debug.c
+++ b/src/amd/vulkan/radv_debug.c
@@ -599,7 +599,7 @@ radv_dump_enabled_options(struct radv_device *device, FILE 
*f)
 
        fprintf(f, "Enabled debug options: ");
 
-       mask = device->debug_flags;
+       mask = device->instance->debug_flags;
        while (mask) {
                int i = u_bit_scan64(&mask);
                fprintf(f, "%s, ", radv_get_debug_option_name(i));
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index e07a573819..d414d8ca85 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1154,8 +1154,6 @@ VkResult radv_CreateDevice(
        device->instance = physical_device->instance;
        device->physical_device = physical_device;
 
-       device->debug_flags = device->instance->debug_flags;
-
        device->ws = physical_device->ws;
        if (pAllocator)
                device->alloc = *pAllocator;
@@ -3151,7 +3149,7 @@ radv_initialise_color_surface(struct radv_device *device,
        }
 
        if (iview->image->cmask.size &&
-           !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
+           !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
                cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
 
        if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index f0645279aa..7c3e55b1b8 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -155,7 +155,7 @@ radv_init_surface(struct radv_device *device,
             (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) ||
             pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1 ||
             device->physical_device->rad_info.chip_class < VI ||
-            create_info->scanout || (device->debug_flags & RADV_DEBUG_NO_DCC))
+            create_info->scanout || (device->instance->debug_flags & 
RADV_DEBUG_NO_DCC))
                surface->flags |= RADEON_SURF_DISABLE_DCC;
        if (create_info->scanout)
                surface->flags |= RADEON_SURF_SCANOUT;
@@ -913,7 +913,7 @@ radv_image_create(VkDevice _device,
        } else {
                /* Otherwise, try to enable HTILE for depth surfaces. */
                if (radv_image_can_enable_htile(image) &&
-                   !(device->debug_flags & RADV_DEBUG_NO_HIZ)) {
+                   !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
                        radv_image_alloc_htile(image);
                        image->tc_compatible_htile = image->surface.flags & 
RADEON_SURF_TC_COMPATIBLE_HTILE;
                } else {
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 0f895f8c50..476a5913ae 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -683,7 +683,7 @@ emit_fast_htile_clear(struct radv_cmd_buffer *cmd_buffer,
        if (!iview->image->surface.htile_size)
                return false;
 
-       if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
+       if (cmd_buffer->device->instance->debug_flags & 
RADV_DEBUG_NO_FAST_CLEARS)
                return false;
 
        if (!radv_layout_is_htile_compressed(iview->image, image_layout, 
radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, 
cmd_buffer->queue_family_index)))
@@ -958,7 +958,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
        if (!iview->image->cmask.size && !iview->image->surface.dcc_size)
                return false;
 
-       if (cmd_buffer->device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS)
+       if (cmd_buffer->device->instance->debug_flags & 
RADV_DEBUG_NO_FAST_CLEARS)
                return false;
 
        if (!radv_layout_can_fast_clear(iview->image, image_layout, 
radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index, 
cmd_buffer->queue_family_index)))
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 0d22bbe4bc..6219ad44ac 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2093,7 +2093,7 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
                pipeline->graphics.vtx_reuse_depth = 14;
        }
 
-       if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
+       if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
                radv_dump_pipeline_stats(device, pipeline);
        }
 
@@ -2198,7 +2198,7 @@ static VkResult radv_compute_pipeline_create(
 
        *pPipeline = radv_pipeline_to_handle(pipeline);
 
-       if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
+       if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
                radv_dump_pipeline_stats(device, pipeline);
        }
        return VK_SUCCESS;
diff --git a/src/amd/vulkan/radv_pipeline_cache.c 
b/src/amd/vulkan/radv_pipeline_cache.c
index 43176b6fdf..625c58e66c 100644
--- a/src/amd/vulkan/radv_pipeline_cache.c
+++ b/src/amd/vulkan/radv_pipeline_cache.c
@@ -60,7 +60,7 @@ radv_pipeline_cache_init(struct radv_pipeline_cache *cache,
        /* We don't consider allocation failure fatal, we just start with a 
0-sized
         * cache. */
        if (cache->hash_table == NULL ||
-           (device->debug_flags & RADV_DEBUG_NO_CACHE))
+           (device->instance->debug_flags & RADV_DEBUG_NO_CACHE))
                cache->table_size = 0;
        else
                memset(cache->hash_table, 0, byte_size);
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 4d2b2c696b..548952faa9 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -513,7 +513,6 @@ struct radv_device {
        struct radv_queue *queues[RADV_MAX_QUEUE_FAMILIES];
        int queue_count[RADV_MAX_QUEUE_FAMILIES];
        struct radeon_winsys_cs *empty_cs[RADV_MAX_QUEUE_FAMILIES];
-       uint64_t debug_flags;
 
        bool llvm_supports_spill;
        bool has_distributed_tess;
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 535d0f4f58..d4bef9792e 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -174,7 +174,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
                uint32_t *spirv = (uint32_t *) module->data;
                assert(module->size % 4 == 0);
 
-               if (device->debug_flags & RADV_DEBUG_DUMP_SPIRV)
+               if (device->instance->debug_flags & RADV_DEBUG_DUMP_SPIRV)
                        radv_print_spirv(spirv, module->size, stderr);
 
                uint32_t num_spec_entries = 0;
@@ -263,7 +263,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
        nir_remove_dead_variables(nir, nir_var_local);
        radv_optimize_nir(nir);
 
-       if (device->debug_flags & RADV_DEBUG_DUMP_SHADERS)
+       if (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS)
                nir_print_shader(nir, stderr);
 
        return nir;
@@ -386,7 +386,7 @@ shader_variant_create(struct radv_device *device,
                      unsigned *code_size_out)
 {
        enum radeon_family chip_family = 
device->physical_device->rad_info.family;
-       bool dump_shaders = device->debug_flags & RADV_DEBUG_DUMP_SHADERS;
+       bool dump_shaders = device->instance->debug_flags & 
RADV_DEBUG_DUMP_SHADERS;
        enum ac_target_machine_options tm_options = 0;
        struct radv_shader_variant *variant;
        struct ac_shader_binary binary;
@@ -458,7 +458,7 @@ radv_shader_variant_create(struct radv_device *device,
        if (key)
                options.key = *key;
 
-       options.unsafe_math = !!(device->debug_flags & RADV_DEBUG_UNSAFE_MATH);
+       options.unsafe_math = !!(device->instance->debug_flags & 
RADV_DEBUG_UNSAFE_MATH);
        options.supports_spill = device->llvm_supports_spill;
 
        return shader_variant_create(device, module, shader, shader->stage,

_______________________________________________
mesa-commit mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/mesa-commit

Reply via email to