Module: Mesa
Branch: master
Commit: 24ec29b919f77116bb61f07bff09cbc14683d23d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=24ec29b919f77116bb61f07bff09cbc14683d23d
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue Jul 25 17:21:22 2017 +0100
i965: perf: list registers to program for queries
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
---
src/mesa/drivers/dri/i965/brw_context.h | 15 ++++++++++
src/mesa/drivers/dri/i965/brw_oa.py | 51 +++++++++++++++++++++++++++++++++
2 files changed, 66 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 0960d635be..766b5bc073 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -615,6 +615,11 @@ enum brw_query_kind {
PIPELINE_STATS
};
+struct brw_perf_query_register_prog {
+ uint32_t reg;
+ uint32_t val;
+};
+
struct brw_perf_query_info
{
enum brw_query_kind kind;
@@ -634,6 +639,16 @@ struct brw_perf_query_info
int a_offset;
int b_offset;
int c_offset;
+
+ /* Register programming for a given query */
+ struct brw_perf_query_register_prog *flex_regs;
+ uint32_t n_flex_regs;
+
+ struct brw_perf_query_register_prog *mux_regs;
+ uint32_t n_mux_regs;
+
+ struct brw_perf_query_register_prog *b_counter_regs;
+ uint32_t n_b_counter_regs;
};
/**
diff --git a/src/mesa/drivers/dri/i965/brw_oa.py
b/src/mesa/drivers/dri/i965/brw_oa.py
index 8c35923462..576ea6687f 100644
--- a/src/mesa/drivers/dri/i965/brw_oa.py
+++ b/src/mesa/drivers/dri/i965/brw_oa.py
@@ -380,6 +380,45 @@ def output_counter_report(set, counter, current_offset):
return current_offset + sizeof(c_type)
+register_types = {
+ 'FLEX': 'flex_regs',
+ 'NOA': 'mux_regs',
+ 'OA': 'b_counter_regs',
+}
+
+def compute_register_lengths(set):
+ register_lengths = {}
+ register_configs = set.findall('register_config')
+ for register_config in register_configs:
+ t = register_types[register_config.get('type')]
+ if t not in register_lengths:
+ register_lengths[t] = len(register_config.findall('register'))
+ else:
+ register_lengths[t] += len(register_config.findall('register'))
+
+ return register_lengths
+
+
+def generate_register_configs(set):
+ register_configs = set.findall('register_config')
+ for register_config in register_configs:
+ t = register_types[register_config.get('type')]
+
+ availability = register_config.get('availability')
+ if availability:
+ output_availability(set, availability, register_config.get('type')
+ ' register config')
+ c_indent(3)
+
+ for register in register_config.findall('register'):
+ c("query->%s[query->n_%s++] = (struct
brw_perf_query_register_prog) { .reg = %s, .val = %s };" %
+ (t, t, register.get('address'), register.get('value')))
+
+ if availability:
+ c_outdent(3)
+ c("}")
+ c("\n")
+
+
def main():
global c_file
global header_file
@@ -475,6 +514,12 @@ def main():
max_values[counter.get('symbol_name')] = output_counter_max(set,
counter, empty_vars)
counter_vars["$" + counter.get('symbol_name')] = counter
+ c("\n")
+ register_lengths = compute_register_lengths(set);
+ for reg_type, reg_length in register_lengths.iteritems():
+ c("static struct brw_perf_query_register_prog
{0}_{1}_{2}[{3}];".format(chipset,
+
set.get('underscore_name'),
+
reg_type, reg_length))
c("\nstatic struct brw_perf_query_counter
{0}_{1}_query_counters[{2}];\n".format(chipset, set.get('underscore_name'),
len(counters)))
c("static struct brw_perf_query_info " + chipset + "_" +
set.get('underscore_name') + "_query = {\n")
@@ -510,6 +555,10 @@ def main():
.c_offset = 46,
"""))
+ for reg_type, reg_length in register_lengths.iteritems():
+ c(".{0} = {1}_{2}_{3},".format(reg_type, chipset,
set.get('underscore_name'), reg_type))
+ c(".n_{0} = 0, /* Determined at runtime */".format(reg_type))
+
c_outdent(3)
c("};\n")
@@ -528,6 +577,8 @@ def main():
c("\nif (!query->data_size) {")
c_indent(3)
+ generate_register_configs(set)
+
offset = 0
for counter in counters:
offset = output_counter_report(set, counter, offset)
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