URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a9aad96aa6d18d5afc20727b1791501cfb7cb48
Author: Rob Clark <[email protected]>
Date: Sat Nov 11 10:50:20 2017 -0500
freedreno/a5xx: fix SSBO emit for non-zero offset
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f25ab4fee3fefc7aad9ed8f9cf101f95a01c51c
Author: Rob Clark <[email protected]>
Date: Sat Nov 11 09:55:00 2017 -0500
freedreno/a5xx: remove obsolete comment
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8fcee858d595f3666e0fc828cce0286342c1d71e
Author: Rob Clark <[email protected]>
Date: Fri Nov 10 12:54:49 2017 -0500
freedreno/ir3: don't create split/fo if only writing .x
In case an instruction only writes one register, and it is .x, we can
skip the extra level of fanout indirection.
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7b2719f69a77b9daad5c17d651b54d98720669f
Author: Rob Clark <[email protected]>
Date: Fri Nov 10 12:53:13 2017 -0500
freedreno/a5xx: indirect grids
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=471aa1b6d03e92d601439cfb2c79a78c12234fdb
Author: Rob Clark <[email protected]>
Date: Thu Nov 9 16:57:05 2017 -0500
freedreno/a5xx: add global size compute cap
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=62981bbe656db1de5311ac5c23a69122748e681b
Author: Rob Clark <[email protected]>
Date: Sun Nov 5 09:15:08 2017 -0500
freedreno/ir3: turn on std430 packing
Seems to fix dEQP compute related tests.. and matches what i965 does, so
perhaps there is some assumption that std430 packing is on by default
somewhere in NIR?
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bedbe7f90c811dcf47975008efbd1b54dbdf2756
Author: Rob Clark <[email protected]>
Date: Sat Nov 4 12:52:43 2017 -0400
freedreno/a5xx: image support
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=819a613ae33410584e13e78e78af82c71716f67d
Author: Rob Clark <[email protected]>
Date: Tue Nov 7 15:12:03 2017 -0500
freedreno/ir3: moar better scheduler
Add a new pass that inserts additional dependencies, rather than simply
relying on SSA srcs added in the nir->ir3 frontend. This makes it
easier to deal with barriers, but the additional false deps also lets us
deal properly with ensuring a write depends on all previous reads.
Since conversion to barrier instructions is lossy (ie. just knowing the
instruction doesn't tell us enough about what other instructions the
barrier applies to), use barrier_class/barrier_conflict fields in the
ir3_instruction to retain this information.
This could probably be relaxed somewhat by considering *which* array/
buffer/image variable is being referenced. Ie. a write to buffer A
can overtake a read from buffer B, if B is not coherent. (right?)
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=15ea8d128ae1b52d419ab5af586c01769276ec9c
Author: Rob Clark <[email protected]>
Date: Thu Nov 9 14:36:06 2017 -0500
freedreno/ir3: move macros
I want to add a growable array to ir3_instruction, so we can append
false dependencies for purposes of scheduling barriers, atomics, and
dealing with write after read hazards.
Just code motion preparing for next patch.
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9edfc369c04d131b664f6c94a0e249a81a5c0da5
Author: Rob Clark <[email protected]>
Date: Thu Nov 9 10:57:55 2017 -0500
freedreno/ir3: image support
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eaae81058cdd0ed103c55be7a1722546d63c86da
Author: Rob Clark <[email protected]>
Date: Thu Nov 9 10:56:43 2017 -0500
freedreno/ir3: shared variable support
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd75abc6f3909a2ed9e8e7c5a533be11c124a509
Author: Rob Clark <[email protected]>
Date: Thu Nov 9 10:48:52 2017 -0500
freedreno/ir3: some SSBO cleanups/fixes
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f8bdf2e2b8cc516b89cd042962d5dab81a695ec
Author: Rob Clark <[email protected]>
Date: Wed Nov 8 18:08:16 2017 -0500
freedreno/ir3: split out INSTR4F instructions
Atomic instructions take a different # of src args depending on .g or .l
variant, split these out into different helpers with INSTR*F() helper
macro that lets you specify instruction flag.
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0038deb256dd17d2c1cc61d7def422a08fef9fd1
Author: Rob Clark <[email protected]>
Date: Wed Nov 8 17:51:40 2017 -0500
freedreno/ir3: cat6 encoding fixes
Instruction encoding/decoding fixes needed for images, shared variables,
etc.
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e9a6c686878e6f41f48c605ff4accbdcf630ef6
Author: Rob Clark <[email protected]>
Date: Tue Oct 31 11:23:15 2017 -0400
freedreno/ir3: add barriers
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c711f4d1898b147b66e1e69b7899d08ec925d0d
Author: Rob Clark <[email protected]>
Date: Tue Oct 31 12:21:51 2017 -0400
freedreno/ir3: invert is_same_type_mov() logic
Some instructions (like barriers) have no dst, which causes problems
with dereferencing a NULL dst. Flip the logic around to reject opc's
that can't be a type of move first, to filter out those instructions.
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6da513007474ddee48edf256e435a0fa7a65335d
Author: Rob Clark <[email protected]>
Date: Mon Oct 30 19:24:59 2017 -0400
freedreno/ir3: add cat7 instructions
Needed for memory and execution barriers.
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=33f5f63b8fc157fa2fd2a142783f31db987c9d55
Author: Rob Clark <[email protected]>
Date: Mon Oct 30 13:23:37 2017 -0400
freedreno/ir3: add SSBO get_buffer_size() support
Somehow I overlooked this when adding initial SSBO support.
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b267a0840443fbccee0b46653a14f3d278490761
Author: Rob Clark <[email protected]>
Date: Mon Oct 30 13:20:17 2017 -0400
freedreno/ir3: extract helper for common consts
User consts and driver consts such as UBO addresses and immediates are
handled the same for all shader stages, so split out a shared helper for
these, to make it easier to add more.
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=13fe1feb627752a0220882b1999bd8597fdbad3b
Author: Rob Clark <[email protected]>
Date: Sat Nov 4 11:14:09 2017 -0400
freedreno: add image view state tracking
It is unfortunate that image state isn't a real CSO, since (at least for
a4xx/a5xx) it is a combination of sampler and "SSBO" image state, and it
would be useful to pre-compute the state block "register" values rather
than doing it at emit time.
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=12c1c3ab2349cff1f9a9be62b7d32b8ed49552b5
Author: Rob Clark <[email protected]>
Date: Tue Oct 31 09:15:08 2017 -0400
freedreno: update generated headers
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0006b860ce83769e3d030ab1fec45a4de04dcadc
Author: Rob Clark <[email protected]>
Date: Fri Nov 3 12:47:51 2017 -0400
mesa/st/nir: assign driver_location for images
Signed-off-by: Rob Clark <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ecbe1e976f279a3519aaf9ab365ebe28b60f1ace
Author: Rob Clark <[email protected]>
Date: Mon Oct 30 09:56:43 2017 -0400
st/program: fix compute shader nir references
In case the IR is NIR, the driver takes reference to the nir_shader.
Also, because there are no variants, we need to clone the shader,
instead of sharing the reference with gl_program, which would result
in a double free in _mesa_delete_program().
Signed-off-by: Rob Clark <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>
Reviewed-by: Timothy Arceri <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5009dc55f206567df1f1527cac06bcbf7cb95814
Author: Rob Clark <[email protected]>
Date: Fri Nov 10 09:04:52 2017 -0500
freedreno/ir3: rename ir3_compile -> ir3_context
Having both an ir3_compile (which was really context for compiling a
single shader variant) and ir3_compiler (which is the compiler object
that compiles all variants, ie. basically holds the RA regset) is a
bit confusing.
Signed-off-by: Rob Clark <[email protected]>
_______________________________________________
mesa-commit mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
