URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9888913a5794435181fef5468efabd3725aece3e
Author: Andres Gomez <[email protected]>
Date: Thu Nov 16 17:30:41 2017 +0200
cherry-ignore: Revert "intel/fs: Use a pure vertical stride for large
register strides"
extra: The commit just references a proper fix that has already
landed.
Signed-off-by: Andres Gomez <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a231bbd639df116691aea3b67d56208b9af6dd21
Author: Andres Gomez <[email protected]>
Date: Fri Nov 17 14:01:36 2017 +0200
cherry-ignore: egl: pass the dri2_dpy to the $plat_teardown functions
fixes: This commit makes reference to 2 other commits but none have
made it to the 17.2 queue.
Signed-off-by: Andres Gomez <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f6d3eed51319d1302f23c69d2fb889988abee984
Author: Andres Gomez <[email protected]>
Date: Sat Nov 11 03:45:34 2017 +0200
cherry-ignore: glsl: Fix typo fragement -> fragment
fixes: This commit is only a typo correction on an error message.
Signed-off-by: Andres Gomez <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba0f965771299fd2bfc677483fa0e1659be47ea2
Author: Andres Gomez <[email protected]>
Date: Sat Nov 11 02:42:37 2017 +0200
cherry-ignore: added 17.3 nominations.
stable: 17.3 nominations only.
Signed-off-by: Andres Gomez <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8cd5bd2a8aeee01c8c83d6676bdb9051d43d9cca
Author: Andres Gomez <[email protected]>
Date: Tue Nov 21 02:14:26 2017 +0200
cherry-ignore: i965: Mark BOs as external when we export their handle
stable: These commits addressed earlier commit 2c4097aff1b which did
not land in branch.
Signed-off-by: Andres Gomez <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=807da6e270fed89e7f281fb68c14235e7fb01c1b
Author: Andres Gomez <[email protected]>
Date: Tue Nov 21 01:48:29 2017 +0200
cherry-ignore: anv/cmd_buffer: Take bo_offset into account in fast clear
state addresses
stable: This commit addressed earlier commit a62a97933578 which did
not land in branch.
Signed-off-by: Andres Gomez <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c9325693f1cb15bbf84470081b97d55df967b6f3
Author: Andres Gomez <[email protected]>
Date: Tue Nov 21 01:45:47 2017 +0200
cherry-ignore: anv/cmd_buffer: Advance the address when initializing clear
colors
stable: This commit depends on earlier commit 3735af04152b which did
not land in branch.
Signed-off-by: Andres Gomez <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1519933ce2702eccad5e4abf70d187116bf4ee6d
Author: Andres Gomez <[email protected]>
Date: Tue Nov 14 17:14:59 2017 +0200
cherry-ignore: r600/shader: reserve first register of vertex shader.
stable: This commit addressed earlier commit ea1b97714d9b which did
not land in branch.
Signed-off-by: Andres Gomez <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d255b77237a19623f8cf48b46dcb2f6f041956e6
Author: Andres Gomez <[email protected]>
Date: Mon Nov 13 23:36:04 2017 +0200
cherry-ignore: intel/fs: refactors
stable: These commits are refactorings rather than fixes.
Signed-off-by: Andres Gomez <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=96be105d4195b223d28e09a23d0e2246b6fbf362
Author: Andres Gomez <[email protected]>
Date: Sat Nov 11 03:29:57 2017 +0200
cherry-ignore: intel/fs: Use the original destination region for int MUL
lowering
stable: These commits resulted in a CTS regression being addressed at
https://bugs.freedesktop.org/show_bug.cgi?id=103626 .
Signed-off-by: Andres Gomez <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=010751e95da1823713c85b886ee80fb92f6a92f7
Author: Andres Gomez <[email protected]>
Date: Sat Nov 11 03:25:33 2017 +0200
cherry-ignore: intel/nir: Use the correct indirect lowering masks in
link_shaders
stable: These commits addressed earlier commit 379b24a40d3 which did
not land in branch.
Signed-off-by: Andres Gomez <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f562d93049df4824bd650419de5af1564f21e081
Author: Andres Gomez <[email protected]>
Date: Wed Nov 15 21:19:57 2017 +0200
cherry-ignore: intel/fs: Use a pure vertical stride for large register
strides
stable: This commit is not really needed after 6ac2d169019.
Signed-off-by: Andres Gomez <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=49277c6e367f33b5badeb25b79b8cc19df98de52
Author: Nicolai Hähnle <[email protected]>
Date: Fri Nov 10 13:11:53 2017 +0100
ddebug: fix use-after-free of streamout targets
Fixes: b47727a83ad6 ("ddebug: implement pipelined hang detection mode")
Reviewed-by: Marek Olšák <[email protected]>
(cherry picked from commit 16f8da299700e714fd5aff265b8f28fe2badfa95)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae629ca8054a55bc4808c06aba1851174a7a42fe
Author: George Barrett <[email protected]>
Date: Sun Nov 19 21:55:10 2017 +1100
glsl: Catch subscripted calls to undeclared subroutines
generate_array_index fails to check whether the target of a subroutine
call exists in the AST, potentially passing around null ir_rvalue
pointers eventuating in abort/segfault.
Fixes: fd01840c0bd3 ("glsl: add AoA support to subroutines")
Reviewed-by: Timothy Arceri <[email protected]>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100438
(cherry picked from commit f09c2cefdd53cd61562a994294e9d0630868d2da)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4456581781de64beaf5928d1f18a91efbb824e3
Author: Kenneth Graunke <[email protected]>
Date: Wed Nov 15 22:40:16 2017 -0800
i965: Upload invariant state once at the start of the batch on Gen4-5.
We want to emit invariant state at the start of a render batch. In the
past, this more or less happened: a new batch flagged BRW_NEW_CONTEXT
(because we don't have hardware contexts), which triggered the
brw_invariant_state atom. So, it would be emitted before any 3D
drawing. (Technically, there might be some BLT commands in the batch
because Gen4-5 have a single combined render/BLT ring, but that should
be harmless).
With the advent of BLORP, this broke. The first item in a batch might
be a BLORP operation, which bypasses the normal draw upload path. So,
we need to ensure invariant state happens first. To do that, we just
upload it when creating a new batch. On Gen6+ we'd need to worry about
whether it's a RENDER or BLT batch, but because we have a combined ring,
this approach should work fine on Gen4-5.
Seems to fix GPU hangs when playing hardware accelerated video with
mpv -hwdec=vaapi on Ironlake.
Cc: [email protected]
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103529
Reviewed-by: Jason Ekstrand <[email protected]>
(cherry picked from commit 8f91aa35a54e127b68415376ef2b577ea8fc30f9)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d02e91c2cd43f0ca0ef658997785b5dddbfb417
Author: Derek Foreman <[email protected]>
Date: Mon Oct 30 15:52:22 2017 -0500
egl/wayland: Add a fallback when fourcc query isn't supported
When queryImage doesn't support __DRI_IMAGE_ATTRIB_FOURCC wayland clients
will die with a NULL derefence in wl_proxy_add_listener.
Attempt to provide a simple fallback to keep ancient systems working.
Fixes: 6595c699511 ("egl/wayland: Remove more surface specifics from
create_wl_buffer")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103519
Signed-off-by: Derek Foreman <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
Acked-by: Daniel Stone <[email protected]>
Reviewed-by: Eric Engestrom <[email protected]>
(cherry picked from commit 0db36caa192b129cb4f22d152f82f38fcf6f06d4)
Squashed with:
egl: fix var type
queryImage() takes an `int*`; compiler is warning about the
signed<->unsigned pointer mismatch.
Fixes: 0db36caa192b129cb4f2 "egl/wayland: Add a fallback when fourcc
query isn't supported"
Signed-off-by: Eric Engestrom <[email protected]>
Reviewed-by: Frank Binns <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
Reviewed-by: Derek Foreman <[email protected]>
(cherry picked from commit ca95d7ad4e1b900eb3d559ed5bda0b96b232961d)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f288607eb76c8ab2afef2bb01405e5b7331e3dc2
Author: Kenneth Graunke <[email protected]>
Date: Tue Nov 14 15:24:36 2017 -0800
i965: Implement another VF cache invalidate workaround on Gen8+.
...and provide a better citation for the existing one.
v2:
- Apply the workaround to Gen8 too, as intended (caught by Topi).
- Restructure to add bits instead of an extra flush (based on a similar
patch by Rafael Antognolli).
Cc: [email protected]
Reviewed-by: Rafael Antognolli <[email protected]>
(cherry picked from commit 8d48671492412e04c18651a779cabacf30ed0afe)
[Andres Gomez: brw->gen not yet dropped in favor of devinfo->gen]
Signed-off-by: Andres Gomez <[email protected]>
Conflicts:
src/mesa/drivers/dri/i965/brw_pipe_control.c
Squashed with:
i965: Revert Gen8 aspect of VF PIPE_CONTROL workaround.
This apparently causes hangs on Broadwell, so let's back it out for now.
I think there are other PIPE_CONTROL workarounds that we're missing.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103787
(cherry picked from commit a01ba366e01b7d1cdfa6b0e6647536b10c0667ef)
[Andres Gomez: brw->gen not yet dropped in favor of devinfo->gen]
Signed-off-by: Andres Gomez <[email protected]>
Conflicts:
src/mesa/drivers/dri/i965/brw_pipe_control.c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3410696e0b700c735e06a5d4d00d6f9c1361621
Author: Matt Turner <[email protected]>
Date: Wed Nov 8 15:14:19 2017 -0800
i965/fs: Split all 32->64-bit MOVs on CHV, BXT, GLK
Fixes the following tests on CHV, BXT, and GLK:
KHR-GL46.shader_ballot_tests.ShaderBallotFunctionBallot
dEQP-VK.spirv_assembly.instruction.compute.uconvert.uint32_to_int64
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103115
(cherry picked from commit cfcfa0b9cd1b1d563a988b1250950057c4612ac9)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=70b1c115b83906987b900a5213a99991b0405da1
Author: Matt Turner <[email protected]>
Date: Fri Nov 10 14:00:24 2017 -0800
i965/fs: Fix extract_i8/u8 to a 64-bit destination
The MOV instruction can extract bytes to words/double words, and
words/double words to quadwords, but not byte to quadwords.
For unsigned byte to quadword, we can read them as words and AND off the
high byte and extract to quadword in one instruction. For signed bytes,
we need to first sign extend to word and the sign extend that word to a
quadword.
Fixes the following test on CHV, BXT, and GLK:
KHR-GL46.shader_ballot_tests.ShaderBallotBitmasks
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103628
Reviewed-by: Jason Ekstrand <[email protected]>
(cherry picked from commit 6ac2d16901927013393f873a34c717ece5014c1a)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=82876e24c45f01e5209b7f8c0ab3430c54b6db28
Author: Anuj Phogat <[email protected]>
Date: Thu Nov 9 11:30:10 2017 -0800
i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW
Number of dwords in MI_FLUSH_DW changed from 4 to 5 in gen8+.
Signed-off-by: Anuj Phogat <[email protected]>
Cc: <[email protected]>
(cherry picked from commit 1dc45d75bb3ff3085f7356b8ec658111529ff76d)
[Andres Gomez: brw->gen not yet dropped in favor of devinfo->gen]
Signed-off-by: Andres Gomez <[email protected]>
Conflicts:
src/mesa/drivers/dri/i965/brw_pipe_control.c
src/mesa/drivers/dri/i965/intel_blit.c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=653a203937e99fbb726b84764418599dff61952f
Author: Anuj Phogat <[email protected]>
Date: Fri Nov 10 14:39:17 2017 -0800
i965: Program DWord Length in MI_FLUSH_DW
Signed-off-by: Anuj Phogat <[email protected]>
Cc: <[email protected]>
(cherry picked from commit 6165fda59b889de035b38d9a1a08ffe0da19e6a6)
Squashed with:
i965: Remove DWord length from MI_FLUSH_DW definition
Fixes: 6165fda59b8 ("i965: Program DWord Length in MI_FLUSH_DW")
Cc: <[email protected]>
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Nanley Chery <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
(cherry picked from commit 822fd2341db49cbbe813114d2d0fc1b66de4807c)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8edbc8f1091595d677621b407c648512437f1dd7
Author: Tim Rowley <[email protected]>
Date: Mon Nov 13 18:39:38 2017 -0600
swr/rast: Faster emulated simd16 permute
Speed up simd16 frontend (default) on avx/avx2 platforms;
fixes performance regression caused by switch to simdlib.
Reviewed-by: Bruce Cherniak <[email protected]>
Cc: [email protected]
(cherry picked from commit d8489517a572c7e5c5405ebf510db9d20b1e2591)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f4dfee254e1f054c851a729deb4217cc4e14003
Author: Tim Rowley <[email protected]>
Date: Mon Nov 13 15:11:21 2017 -0600
swr/rast: Use gather instruction for i32gather_ps on simd16/avx512
Speed up avx512 platforms; fixes performance regression caused
by swithc to simdlib.
Reviewed-by: Bruce Cherniak <[email protected]>
Cc: [email protected]
(cherry picked from commit 439904847e9c2970494c18e8c47bd6c38c0ed8ab)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=256733683b70731235eeac94e95d66e9d8a3c56e
Author: Bas Nieuwenhuizen <[email protected]>
Date: Mon Nov 13 23:26:32 2017 +0100
radv: Free temporary syncobj after waiting on it.
Otherwise we leak it.
Fixes: eaa56eab6da "radv: initial support for shared semaphores (v2)"
Reviewed-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 7c255788637b8fdfc31aca5f7891f39a110c5cb2)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=75efb540e2a2e7631f1724550fffe37a9fcf48dc
Author: Bas Nieuwenhuizen <[email protected]>
Date: Mon Nov 13 23:18:19 2017 +0100
radv: Free syncobj with multiple imports.
Otherwise we can leak the old syncobj.
Fixes: eaa56eab6da "radv: initial support for shared semaphores (v2)"
Reviewed-by: Dave Airlie <[email protected]>
Reviewed-by: Samuel Pitoiset <[email protected]>
(cherry picked from commit 917d3b43f2b206ccf036542aa1c39f1dbdd84f62)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=179acf6579478bea3fbb2f2d23fc436bb7d8f55b
Author: Jason Ekstrand <[email protected]>
Date: Fri Nov 3 15:57:47 2017 -0700
i965: Add stencil buffers to cache set regardless of stencil texturing
We may access them as a texture using blorp regardless of whether or not
stencil texturing is enabled.
Reviewed-by: Kenneth Graunke <[email protected]>
Cc: [email protected]
(cherry picked from commit 6830ba0d3be8df12572622839743c41b4f294825)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=84f765ce25226c2d7694ff42d0f761310bdcb7b9
Author: Dave Airlie <[email protected]>
Date: Mon Nov 13 15:40:15 2017 +1000
r600: fix isoline tess factor component swapping.
As per radeonsi, the tess factor components for isolines
are reversed.
Fixes: tests/spec/arb_tessellation_shader/execution/isoline.shader_test
Cc: <[email protected]>
Signed-off-by: Dave Airlie <[email protected]>
(cherry picked from commit f3f8615d76b20ad66466b172a600e06b9a833729)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0465cfe0b0c8c846fc5428123c93bfe5a04b0888
Author: Kenneth Graunke <[email protected]>
Date: Fri Nov 10 15:36:22 2017 -0800
intel/tools: Fix detection of enabled shader stages.
We renamed "Function Enable" to "Enable", which broke our detection
of whether shaders are enabled or not. So, we'd see a bunch of HS/DS
packets with program offsets of 0, and think that was a valid TCS/TES.
Fixes: c032cae9ff77e (genxml: Rename "Function Enable" to "Enable".)
Reviewed-by: Lionel Landwerlin <[email protected]>
(cherry picked from commit 9a0465b3a3a1a6e8beda7a59506c2e1a1aae776f)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9229774b86f7c62c576b2308b971f0cd92e194c7
Author: Kenneth Graunke <[email protected]>
Date: Thu Nov 9 00:06:14 2017 -0800
i965: Make L3 configuration atom listen for TCS/TES program updates.
The L3 configuration code already considers the TCS and TES programs,
but failed to listen for TCS/TES program changes.
This was somehow missing.
Fixes: e9644cb1f96ccf7e ("i965: Consider tessellation in
get_pipeline_state_l3_weights.")
Reviewed-by: Francisco Jerez <[email protected]>
(cherry picked from commit b8d42cccd053e32ca048645ea7e6f901366e286d)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5e82045cad8d9eb6d0124cfe6d9809eac36d9d8
Author: Dylan Baker <[email protected]>
Date: Thu Nov 9 13:49:52 2017 -0800
autotools: Set C++ visibility flags on Intel
These flags are set for C sources, but not C++. This causes symbol
visibility leaks from the C++ parts of the Intel compiler.
Fixes: 700bebb958e93f4d ("i965: Move the back-end compiler to
src/intel/compiler")
Signed-off-by: Dylan Baker <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
(cherry picked from commit 854455498c0370e959c0bb25680641e05faea3e2)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=167f50ae68867eb63f18a82d7fec21bf75ab399f
Author: Adam Jackson <[email protected]>
Date: Thu Nov 9 16:57:31 2017 -0500
glx/dri3: Fix passing renderType into glXCreateContext
Without this, trying to create a GLX_RGBA_FLOAT_TYPE_ARB context would
fail, because GLX_RGBA_TYPE would be a mismatch with the fbconfig.
Cc: [email protected]
Reviewed-by: Tapani Pälli <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
Signed-off-by: Adam Jackson <[email protected]>
(cherry picked from commit 257edb5b9aedc9fc5d5c13eb2f48a0c11d15456f)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d53558fd67f1b7bbcc4fa9cb40f8c572d752b5dc
Author: Adam Jackson <[email protected]>
Date: Thu Nov 9 16:57:30 2017 -0500
glx/drisw: Fix glXMakeCurrent(dpy, None, ctx)
This is perfectly legal in GL 3.0+.
Fixes piglit/glx-create-context-current-no-framebuffer.
Cc: [email protected]
Reviewed-by: Tapani Pälli <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
Signed-off-by: Adam Jackson <[email protected]>
(cherry picked from commit 033cfb17db85b38bc012d74f30f6c92cddf85216)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c9d72046f43d7f81722bee113eb097d2d7121c9
Author: Alex Smith <[email protected]>
Date: Tue Nov 7 10:52:48 2017 +0000
nir/spirv: tg4 requires a sampler
Gather operations in both GLSL and SPIR-V require a sampler. Fixes
gathers returning garbage when using separate texture/samplers (on AMD,
was using an invalid sampler descriptor).
Signed-off-by: Alex Smith <[email protected]>
Cc: "17.2 17.3" <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
(cherry picked from commit 4122d008466cef47eaa3f958924618060f4e4330)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d49fd747c7925326380cc25daf44ee49a10f18a
Author: Alex Smith <[email protected]>
Date: Mon Nov 6 10:37:05 2017 +0000
spirv: Use correct type for sampled images
We should use the result type of the OpSampledImage opcode, rather than
the type of the underlying image/samplers.
This resolves an issue when using separate images and shadow samplers
with glslang. Example:
layout (...) uniform samplerShadow s0;
layout (...) uniform texture2D res0;
...
float result = textureLod(sampler2DShadow(res0, s0), uv, 0);
For this, for the combined OpSampledImage, the type of the base image
was being used (which does not have the Depth flag set, whereas the
result type does), therefore it was not being recognised as a shadow
sampler. This led to the wrong LLVM intrinsics being emitted by RADV.
Signed-off-by: Alex Smith <[email protected]>
Cc: "17.2 17.3" <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
(cherry picked from commit e9eb3c4753e4f56b03d16d8d6f71d49f1e7b97db)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a3adb7389371bf7fbb3341139d959f3c73a241b1
Author: Emil Velikov <[email protected]>
Date: Tue Oct 31 18:58:10 2017 +0000
configure.ac: require xcb* for the omx/va/... when using x11 platform
Targets such as omx and va can work w/o anything X related. Mandate the
xcb* dependencies only when the X11 platform is selected.
Reported-by: Lukas Rusak <[email protected]>
Fixes: 63e11ac2b5c ("configure: error out if building VA w/o supported
platform")
Signed-off-by: Emil Velikov <[email protected]>
Reviewed-by: Eric Engestrom <[email protected]>
Tested-by: Lukas Rusak <[email protected]> (v1)
(cherry picked from commit 85a017230cacd0661570421c8e5b0619e512d33d)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c7e12a3afc0e5fb16e6cb5c2888e7bf2e0addb6d
Author: Emil Velikov <[email protected]>
Date: Tue Oct 31 18:58:09 2017 +0000
configure.ac: loosen --enable-glvnd check to honour egl
Currently we error out when building GLVND w/o GLX.
That was the original premice before we had EGL. As the commit says,
that error should be reworked to honour both - do so.
v2: Drop noop *);; (Eric)
Reported-by: Lukas Rusak <[email protected]>
Fixes: ce562f9e3fa ("EGL: Implement the libglvnd interface for EGL (v3)")
Signed-off-by: Emil Velikov <[email protected]>
Reviewed-by: Eric Engestrom <[email protected]>
Tested-by: Lukas Rusak <[email protected]> (v1)
(cherry picked from commit b4967561c035182b64d3ae0f474d4ef281535ce1)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ca2b0079906f591498c32fde97ed91ade08ff74
Author: Neil Roberts <[email protected]>
Date: Mon Oct 30 13:22:49 2017 +0100
glsl: Transform fb buffers are only active if a variable uses them
The GL spec will soon be revised to clarify that a buffer binding for
a transform feedback buffer is only required if a variable is actually
defined to use the buffer binding point. Previously a declaration for
the default transform buffer would make it require a binding even if
nothing was declared to use the default buffer.
Affects:
KHR-GL44/45.enhanced_layouts.xfb_stride_of_empty_list
KHR-GL44/45.enhanced_layouts.xfb_stride_of_empty_list_and_api
Reviewed-by: Nicolai Hähnle <[email protected]>
Cc: [email protected]
(cherry picked from commit 4dc8458cd13154daa48bd97c3f8393daf02aa351)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=731076f0fd45e21fe1328e53828deb2071d77168
Author: Timothy Arceri <[email protected]>
Date: Wed Nov 8 10:57:21 2017 +1100
mesa: rework how we free gl_shader_program_data
When I introduced gl_shader_program_data one of the intentions was to
fix a bug where a failed linking attempt freed data required by a
currently active program. However I seem to have failed to finish
hooking up the final steps required to have the data hang around.
Here we create a fresh instance of gl_shader_program_data every
time we link. gl_program has a reference to gl_shader_program_data
so it will be freed once the program is no longer active.
Cc: "17.2 17.3" <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]>
Reviewed-by: Neil Roberts <[email protected]>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102177
(cherry picked from commit 6a72eba755fea15a0d97abb913a6315d9d32e274)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=96fe2da88b4307a5ecf556d34fbe9a94d1256466
Author: Timothy Arceri <[email protected]>
Date: Wed Nov 8 11:34:10 2017 +1100
glsl: use the correct parent when allocating program data members
Cc: "17.2 17.3" <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
(cherry picked from commit 9c33533586476693a197b7179552d140d54f23f2)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=386cc0c6a844300f6505cbbe0d5ce75e00e65805
Author: Timothy Arceri <[email protected]>
Date: Wed Nov 8 09:54:22 2017 +1100
glsl: drop cache_fallback
This turned out to be a dead end, it is much easier and less error
prone to just cache the IR used by the drivers backend e.g. TGSI or
NIR.
Cc: "17.2 17.3" <[email protected]>
Reviewed-by: Tapani Pälli <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
(cherry picked from commit cf05bb506a075c9e3b8a3c374b928ff0367c49b2)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dfa57d01e4ffc3707da192c17488330773f9a6c9
Author: Kenneth Graunke <[email protected]>
Date: Tue Oct 31 00:56:24 2017 -0700
i965: properly initialize brw->cs.base.stage to MESA_SHADER_COMPUTE
This has a bit of a surprising effect:
For the render pipeline, the upload_sampler_state_table atom emits
3DSTATE_BINDING_TABLE_POINTERS_XS. It tries to avoid this for compute:
if (GEN_GEN >= 7 && stage_state->stage != MESA_SHADER_COMPUTE) {
/* Emit a 3DSTATE_SAMPLER_STATE_POINTERS_XS packet. */
genX(emit_sampler_state_pointers_xs)(brw, stage_state);
} ...
However, we were failing to initialize brw->cs.base.stage, so it was
left as 0 (MESA_SHADER_VERTEX), causing this condition to break. We
then emitted 3DSTATE_SAMPLER_STATE_POINTERS_VS in GPGPU mode, when
trying to upload CS samplers. Nothing good can come of this.
Found by inspection while debugging a GPU hang. Jordan believes this
helps the Deus Ex: Mankind Divided benchmark mode's stability when
running with shader cache.
Cc: [email protected]
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Jordan Justen <[email protected]>
(cherry picked from commit a16dc04ad51c32e5c7d136e4dd6273d983385d3f)
[Andres Gomez: resolve trivial conflicts]
Signed-off-by: Andres Gomez <[email protected]>
Conflicts:
src/mesa/drivers/dri/i965/brw_context.c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7d61bf508508f382b5811f91ab07673af8119e17
Author: Emil Velikov <[email protected]>
Date: Mon Oct 16 16:40:07 2017 +0100
targets/opencl: don't hardcode the icd file install to /etc/...
Use $(sysconfdir) instead of hardcoding /etc.
While the OpenCL spec expects the file in /etc, people building their
stack can override that, esp. !Linux users.
Furthermore this removes a fundamental violation, which results in the
system file being overwritten even as one explicitly sets --prefix
and/or DESTDIR.
Cc: [email protected]
Signed-off-by: Emil Velikov <[email protected]>
Reviewed-by: Francisco Jerez <[email protected]>
Reviewed-By: Aaron Watry <[email protected]>
(cherry picked from commit 0cd09585441d15ef1ff49de497008103f0b0e1ac)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=61401e971aae55e574112fcedb6f8416ebae0cae
Author: Jason Ekstrand <[email protected]>
Date: Fri Sep 1 09:59:34 2017 -0700
intel/fs: Rework zero-length URB write handling
Originally we tried to handle this case based on slots_valid. However,
there are a number of ways that this can go wrong. For one, we throw
away any trailing slots which either aren't written or are set to
VARYING_SLOT_PAD. Second, even if PSIZ is a valid slot, we may not
actually write anything there. Between the lot of these, it was
possible to end up in a case where we tried to do a regular URB write
but ended up with a length of 1 which is invalid. This commit moves it
to the end and makes it based on a new boolean flag urb_written.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Cc: [email protected]
(cherry picked from commit 7a82ad54bb56cafaeea7f909cd9fc35542c23ba0)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a2230871bfb5e69d932dc959fce8db60eb47c071
Author: Jason Ekstrand <[email protected]>
Date: Mon Oct 2 20:25:11 2017 -0700
intel/fs: Mark 64-bit values as being contiguous
This isn't often a problem , when we're in a compute shader, we must
push the thread local ID so we decrement the amount of available push
space by 1 and it's no longer even and 64-bit data can, in theory, span
it. By marking those uniforms contiguous, we ensure that they never get
split in half between push and pull constants.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Cc: [email protected]
(cherry picked from commit 25f7453c9e6dc7c947b936bdac86680c332362bf)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a868bd7a7c1c58844fe11925c4f66f096c4a1916
Author: Jason Ekstrand <[email protected]>
Date: Tue Oct 17 18:56:29 2017 -0700
intel/fs: Fix integer multiplication lowering for src/dst hazards
Reviewed-by: Iago Toral Quiroga <[email protected]>
Cc: [email protected]
(cherry picked from commit d54f8ec744545673fd78f15ffce3cb4e47d4b5f1)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb14fb271974aafb0b50cd5291aa6cfdf43ef978
Author: Jason Ekstrand <[email protected]>
Date: Tue Oct 17 14:45:43 2017 -0700
intel/fs: Fix MOV_INDIRECT for 64-bit values on little-core
The same workaround we need for 64-bit values on little core also takes
care of the Ivy Bridge problem and does so a bit more efficiently so we
can drop that code while we're here.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Cc: [email protected]
(cherry picked from commit fd1bcccc2de9ba6a1ad6171342a155091963c3b9)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=73342c304d608e1a0180d19c5de50b177e27bdf7
Author: Jason Ekstrand <[email protected]>
Date: Tue Oct 17 19:50:36 2017 -0700
intel/eu/reg: Add a subscript() helper
This is similar to the identically named fs_reg helper.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Cc: [email protected]
(cherry picked from commit 10e4feed39120072f38274b95e884422f72f360f)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=00ccd7856e5c3640e2a496a36b4094d1ae893fb6
Author: Jason Ekstrand <[email protected]>
Date: Thu Oct 12 16:17:03 2017 -0700
intel/fs: Use a pair of 1-wide MOVs instead of SEL for any/all
For some reason, the any/all predicates don't work properly with SIMD32.
In particular, it appears that a SEL with a QtrCtrl of 2H doesn't read
the correct subset of the flag register and you end up getting garbage
in the second half. Work around this by using a pair of 1-wide MOVs and
scattering the result. This fixes the any/all instructions for SIMD32.
Reviewed-by: Matt Turner <[email protected]>
Cc: [email protected]
(cherry picked from commit 1b8ef49f48ae3634e4903422a9d9c11864c03cb1)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=952225ae3783eb6321c7baa8cbb06d5b987a2605
Author: Jason Ekstrand <[email protected]>
Date: Wed Sep 6 20:32:30 2017 -0700
intel/fs: Use an explicit D type for vote any/all/eq intrinsics
The any/all intrinsics return a boolean value so D or UD is the correct
type. Unfortunately, get_nir_dest has the annoying behavior of
returnning a float type by default. This causes format conversion which
gives us -1.0f or 0.0f in the register. If the consumer of the result
does an integer comparison to zero, it will give you the right boolean
value but if we do something more clever based on the 0/~0 assumption
for booleans, this will give the wrong value.
Reviewed-by: Iago Toral Quiroga <[email protected]>
Cc: [email protected]
(cherry picked from commit 1f416630079f38110910ba796f70e2b81e9ddbf4)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=977cd76f103d5665feae46ac7b1c4d53d25bb833
Author: Jason Ekstrand <[email protected]>
Date: Fri Sep 1 23:24:15 2017 -0700
intel/fs: Use ANY/ALL32 predicates in SIMD32
We have ANY/ALL32 predicates and, for the most part, they work just
fine. (See the next commit for more details.) Also, due to the way
that flag registers are handled in hardware, instruction splitting is
able to split the CMP correctly. Specifically, that hardware looks at
the execution group and knows to shift it's flag usage up correctly so a
2H instruction will write to f0.1 instead of f0.0.
Reviewed-by: Matt Turner <[email protected]>
Cc: [email protected]
(cherry picked from commit def013a863558a1f4735d82ef3dfa0f8261fa743)
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