Module: Mesa Branch: master Commit: b1ce812c514750f8d94a6813df351a9e5430825d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1ce812c514750f8d94a6813df351a9e5430825d
Author: Kevin Rogovin <kevin.rogo...@intel.com> Date: Tue Dec 12 14:17:27 2017 +0200 i965: compute scratch space size correctly for Gen9+ Fixes: 8ecdbb61360 "i965: Pretend there are 4 subslices for compute shader threads on Gen9+." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104005 Signed-off-by: Kevin Rogovin <kevin.rogo...@intel.com> Reviewed-by: Kenneth Graunke <kenn...@whitecape.org> Tested-by: Eero Tamminen <eero.t.tammi...@intel.com> --- src/mesa/drivers/dri/i965/brw_program.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index 6aa41009e7..5b168c25e3 100644 --- a/src/mesa/drivers/dri/i965/brw_program.c +++ b/src/mesa/drivers/dri/i965/brw_program.c @@ -368,9 +368,13 @@ brw_alloc_stage_scratch(struct brw_context *brw, * * According to the other driver team, this applies to compute shaders * as well. This is not currently documented at all. + * + * brw->screen->subslice_total is the TOTAL number of subslices + * and we wish to view that there are 4 subslices per slice + * instead of the actual number of subslices per slice. */ if (devinfo->gen >= 9) - subslices = 4; + subslices = 4 * brw->screen->devinfo.num_slices; /* WaCSScratchSize:hsw * _______________________________________________ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
