Module: Mesa
Branch: master
Commit: 0536737983981b03fbe8bccd9f3a0f7ae81479b0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0536737983981b03fbe8bccd9f3a0f7ae81479b0
Author: Rob Clark <robdcl...@gmail.com>
Date: Mon Dec 18 13:34:18 2017 -0500
freedreno/a5xx: use vertex_id_zero_base
Cmdstream traces from blob make it clear that the blob driver dev's
*think* a5xx has a real (non-zero-based) vtxid. But reality claims
differently.
Fixes ./bin/gl-3.2-basevertex-vertexid and probably others.
This means draw-indirect is going to need some gymnastics to copy
base-vertex into uniform. (a4xx probably needs that too.)
Signed-off-by: Rob Clark <robdcl...@gmail.com>
---
src/gallium/drivers/freedreno/a5xx/fd5_program.c | 2 +-
src/gallium/drivers/freedreno/ir3/ir3_nir.c | 19 -------------------
2 files changed, 1 insertion(+), 20 deletions(-)
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_program.c
b/src/gallium/drivers/freedreno/a5xx/fd5_program.c
index aa4babdf5b..81fe7d4b58 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_program.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_program.c
@@ -341,7 +341,7 @@ fd5_program_emit(struct fd_context *ctx, struct
fd_ringbuffer *ring,
pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
- vertex_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID);
+ vertex_regid = ir3_find_sysval_regid(s[VS].v,
SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
instance_regid = ir3_find_sysval_regid(s[VS].v,
SYSTEM_VALUE_INSTANCE_ID);
if (s[FS].v->color0_mrt) {
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_nir.c
b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
index 39d3bf15fd..9ab5e0f7f2 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_nir.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_nir.c
@@ -52,23 +52,6 @@ static const nir_shader_compiler_options options = {
.lower_extract_word = true,
};
-static const nir_shader_compiler_options options_5xx = {
- .lower_fpow = true,
- .lower_fsat = true,
- .lower_scmp = true,
- .lower_flrp32 = true,
- .lower_flrp64 = true,
- .lower_ffract = true,
- .lower_fmod32 = true,
- .lower_fmod64 = true,
- .lower_fdiv = true,
- .fuse_ffma = true,
- .native_integers = true,
- .vertex_id_zero_based = false,
- .lower_extract_byte = true,
- .lower_extract_word = true,
-};
-
struct nir_shader *
ir3_tgsi_to_nir(const struct tgsi_token *tokens)
{
@@ -78,8 +61,6 @@ ir3_tgsi_to_nir(const struct tgsi_token *tokens)
const nir_shader_compiler_options *
ir3_get_compiler_options(struct ir3_compiler *compiler)
{
- if (compiler->gpu_id >= 500)
- return &options_5xx;
return &options;
}
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