Module: Mesa
Branch: master
Commit: 52056206e171f8eec0afc16cfd90ee68bf290e7b
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=52056206e171f8eec0afc16cfd90ee68bf290e7b

Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date:   Wed Feb 21 13:07:10 2018 -0800

anv: Don't assert that stencil HiZ clears are single-slice

It's true for depth HiZ clears because we only have HiZ on single-slice
images right now.  However, for stencil-only clears there is no such
restriction.

Tested-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Nanley Chery <nanley.g.ch...@intel.com>

---

 src/intel/vulkan/genX_cmd_buffer.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 8015a42c15..ce546249b3 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -3438,9 +3438,12 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer 
*cmd_buffer,
                                                      
VK_IMAGE_ASPECT_STENCIL_BIT)) {
          if (att_state->fast_clear) {
             /* We currently only support HiZ for single-layer images */
-            assert(iview->planes[0].isl.base_level == 0);
-            assert(iview->planes[0].isl.base_array_layer == 0);
-            assert(fb->layers == 1);
+            if (att_state->pending_clear_aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
+               assert(iview->image->planes[0].aux_usage == ISL_AUX_USAGE_HIZ);
+               assert(iview->planes[0].isl.base_level == 0);
+               assert(iview->planes[0].isl.base_array_layer == 0);
+               assert(fb->layers == 1);
+            }
 
             anv_image_hiz_clear(cmd_buffer, image,
                                 att_state->pending_clear_aspects,

_______________________________________________
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit

Reply via email to