Module: Mesa Branch: master Commit: 227edf05f34ed38a3f7829d716c988eff5f7d271 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=227edf05f34ed38a3f7829d716c988eff5f7d271
Author: Rafael Antognolli <[email protected]> Date: Wed Mar 21 11:42:21 2018 -0700 intel/genxml: Add ROW_INSTDONE register. Reviewed-by: Lionel Landwerlin <[email protected]> --- src/intel/genxml/gen10.xml | 18 ++++++++++++++++++ src/intel/genxml/gen11.xml | 18 ++++++++++++++++++ src/intel/genxml/gen7.xml | 20 ++++++++++++++++++++ src/intel/genxml/gen75.xml | 22 ++++++++++++++++++++++ src/intel/genxml/gen8.xml | 18 ++++++++++++++++++ src/intel/genxml/gen9.xml | 18 ++++++++++++++++++ 6 files changed, 114 insertions(+) diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml index e0bf0e9159..afdb580b62 100644 --- a/src/intel/genxml/gen10.xml +++ b/src/intel/genxml/gen10.xml @@ -3486,6 +3486,24 @@ <field name="SFBE Done" start="25" end="25" type="bool"/> </register> + <register name="ROW_INSTDONE" length="1" num="0xe164"> + <field name="BC Done" start="0" end="0" type="bool"/> + <field name="PSD Done" start="1" end="1" type="bool"/> + <field name="DAPR Done" start="3" end="3" type="bool"/> + <field name="TDL Done" start="6" end="6" type="bool"/> + <field name="IC Done" start="12" end="12" type="bool"/> + <field name="MA0 Done" start="15" end="15" type="bool"/> + <field name="EU00 Done SS0" start="16" end="16" type="bool"/> + <field name="EU01 Done SS0" start="17" end="17" type="bool"/> + <field name="EU02 Done SS0" start="18" end="18" type="bool"/> + <field name="EU03 Done SS0" start="19" end="19" type="bool"/> + <field name="EU10 Done SS0" start="21" end="21" type="bool"/> + <field name="EU11 Done SS0" start="22" end="22" type="bool"/> + <field name="EU12 Done SS0" start="23" end="23" type="bool"/> + <field name="EU13 Done SS0" start="24" end="24" type="bool"/> + <field name="MA1 Done SS0" start="26" end="26" type="bool"/> + </register> + <register name="L3CNTLREG" length="1" num="0x7034"> <field name="SLM Enable" start="0" end="0" type="uint"/> <field name="URB Allocation" start="1" end="7" type="uint"/> diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml index 3278f35b82..a5e67c30bf 100644 --- a/src/intel/genxml/gen11.xml +++ b/src/intel/genxml/gen11.xml @@ -3482,6 +3482,24 @@ <field name="SFBE Done" start="25" end="25" type="bool"/> </register> + <register name="ROW_INSTDONE" length="1" num="0xe164"> + <field name="BC Done" start="0" end="0" type="bool"/> + <field name="PSD Done" start="1" end="1" type="bool"/> + <field name="DAPR Done" start="3" end="3" type="bool"/> + <field name="TDL Done" start="6" end="6" type="bool"/> + <field name="IC Done" start="12" end="12" type="bool"/> + <field name="MA0 Done" start="15" end="15" type="bool"/> + <field name="EU00 Done SS0" start="16" end="16" type="bool"/> + <field name="EU01 Done SS0" start="17" end="17" type="bool"/> + <field name="EU02 Done SS0" start="18" end="18" type="bool"/> + <field name="EU03 Done SS0" start="19" end="19" type="bool"/> + <field name="EU10 Done SS0" start="21" end="21" type="bool"/> + <field name="EU11 Done SS0" start="22" end="22" type="bool"/> + <field name="EU12 Done SS0" start="23" end="23" type="bool"/> + <field name="EU13 Done SS0" start="24" end="24" type="bool"/> + <field name="MA1 Done SS0" start="26" end="26" type="bool"/> + </register> + <register name="L3CNTLREG" length="1" num="0x7034"> <field name="SLM Enable" start="0" end="0" type="uint"/> <field name="URB Allocation" start="1" end="7" type="uint"/> diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml index bc9fa5b65d..52ca043b51 100644 --- a/src/intel/genxml/gen7.xml +++ b/src/intel/genxml/gen7.xml @@ -2416,6 +2416,26 @@ <field name="VSC Done" start="16" end="16" type="bool"/> </register> + <register name="ROW_INSTDONE" length="1" num="0xe164"> + <field name="BC Done" start="0" end="0" type="bool"/> + <field name="PSD Done" start="1" end="1" type="bool"/> + <field name="DC Done" start="2" end="2" type="bool"/> + <field name="DAPR Done" start="3" end="3" type="bool"/> + <field name="TDL Done" start="6" end="6" type="bool"/> + <field name="GW Done" start="8" end="8" type="bool"/> + <field name="IC Done" start="12" end="12" type="bool"/> + <field name="EU00 Done SS0" start="16" end="16" type="bool"/> + <field name="EU01 Done SS0" start="17" end="17" type="bool"/> + <field name="EU02 Done SS0" start="18" end="18" type="bool"/> + <field name="EU03 Done SS0" start="19" end="19" type="bool"/> + <field name="MA0 Done SS0" start="20" end="20" type="bool"/> + <field name="EU10 Done SS0" start="21" end="21" type="bool"/> + <field name="EU11 Done SS0" start="22" end="22" type="bool"/> + <field name="EU12 Done SS0" start="23" end="23" type="bool"/> + <field name="EU13 Done SS0" start="24" end="24" type="bool"/> + <field name="MA1 Done" start="25" end="25" type="bool"/> + </register> + <register name="L3SQCREG1" length="1" num="0xb010"> <field name="Convert DC_UC" start="24" end="24" type="uint"/> <field name="Convert IS_UC" start="25" end="25" type="uint"/> diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml index 9e2b789006..9501ec53f8 100644 --- a/src/intel/genxml/gen75.xml +++ b/src/intel/genxml/gen75.xml @@ -2886,6 +2886,28 @@ <field name="SARB Done" start="15" end="15" type="bool"/> </register> + <register name="ROW_INSTDONE" length="1" num="0xe164"> + <field name="BC Done" start="0" end="0" type="bool"/> + <field name="PSD Done" start="1" end="1" type="bool"/> + <field name="DC Done" start="2" end="2" type="bool"/> + <field name="DAPR Done" start="3" end="3" type="bool"/> + <field name="TDL Done" start="6" end="6" type="bool"/> + <field name="GW Done" start="8" end="8" type="bool"/> + <field name="IC Done" start="12" end="12" type="bool"/> + <field name="MA0 Done" start="15" end="15" type="bool"/> + <field name="EU00 Done SS0" start="16" end="16" type="bool"/> + <field name="EU01 Done SS0" start="17" end="17" type="bool"/> + <field name="EU02 Done SS0" start="18" end="18" type="bool"/> + <field name="EU03 Done SS0" start="19" end="19" type="bool"/> + <field name="EU04 Done SS0" start="20" end="20" type="bool"/> + <field name="EU10 Done SS0" start="21" end="21" type="bool"/> + <field name="EU11 Done SS0" start="22" end="22" type="bool"/> + <field name="EU12 Done SS0" start="23" end="23" type="bool"/> + <field name="EU13 Done SS0" start="24" end="24" type="bool"/> + <field name="EU14 Done SS0" start="25" end="25" type="bool"/> + <field name="MA1 Done SS0" start="26" end="26" type="bool"/> + </register> + <register name="L3SQCREG1" length="1" num="0xb010"> <field name="Convert DC_UC" start="24" end="24" type="uint"/> <field name="Convert IS_UC" start="25" end="25" type="uint"/> diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml index 0a6be59698..10dc787f48 100644 --- a/src/intel/genxml/gen8.xml +++ b/src/intel/genxml/gen8.xml @@ -3147,6 +3147,24 @@ <field name="TDC Done" start="24" end="24" type="bool"/> </register> + <register name="ROW_INSTDONE" length="1" num="0xe164"> + <field name="BC Done" start="0" end="0" type="bool"/> + <field name="PSD Done" start="1" end="1" type="bool"/> + <field name="DAPR Done" start="3" end="3" type="bool"/> + <field name="TDL Done" start="6" end="6" type="bool"/> + <field name="IC Done" start="12" end="12" type="bool"/> + <field name="MA0 Done" start="15" end="15" type="bool"/> + <field name="EU00 Done SS0" start="16" end="16" type="bool"/> + <field name="EU01 Done SS0" start="17" end="17" type="bool"/> + <field name="EU02 Done SS0" start="18" end="18" type="bool"/> + <field name="EU03 Done SS0" start="19" end="19" type="bool"/> + <field name="EU10 Done SS0" start="21" end="21" type="bool"/> + <field name="EU11 Done SS0" start="22" end="22" type="bool"/> + <field name="EU12 Done SS0" start="23" end="23" type="bool"/> + <field name="EU13 Done SS0" start="24" end="24" type="bool"/> + <field name="MA1 Done SS0" start="26" end="26" type="bool"/> + </register> + <register name="L3CNTLREG" length="1" num="0x7034"> <field name="SLM Enable" start="0" end="0" type="uint"/> <field name="URB Allocation" start="1" end="7" type="uint"/> diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml index 834f5773ff..90d3a15eb2 100644 --- a/src/intel/genxml/gen9.xml +++ b/src/intel/genxml/gen9.xml @@ -3432,6 +3432,24 @@ <field name="TDC Done" start="24" end="24" type="bool"/> </register> + <register name="ROW_INSTDONE" length="1" num="0xe164"> + <field name="BC Done" start="0" end="0" type="bool"/> + <field name="PSD Done" start="1" end="1" type="bool"/> + <field name="DAPR Done" start="3" end="3" type="bool"/> + <field name="TDL Done" start="6" end="6" type="bool"/> + <field name="IC Done" start="12" end="12" type="bool"/> + <field name="MA0 Done" start="15" end="15" type="bool"/> + <field name="EU00 Done SS0" start="16" end="16" type="bool"/> + <field name="EU01 Done SS0" start="17" end="17" type="bool"/> + <field name="EU02 Done SS0" start="18" end="18" type="bool"/> + <field name="EU03 Done SS0" start="19" end="19" type="bool"/> + <field name="EU10 Done SS0" start="21" end="21" type="bool"/> + <field name="EU11 Done SS0" start="22" end="22" type="bool"/> + <field name="EU12 Done SS0" start="23" end="23" type="bool"/> + <field name="EU13 Done SS0" start="24" end="24" type="bool"/> + <field name="MA1 Done SS0" start="26" end="26" type="bool"/> + </register> + <register name="L3CNTLREG" length="1" num="0x7034"> <field name="SLM Enable" start="0" end="0" type="uint"/> <field name="URB Allocation" start="1" end="7" type="uint"/> _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
