Mesa (master): freedreno: a2xx: Implement DP2 instruction

[Rob Clark]

Module: Mesa
Branch: master
Commit: e8e3aa68d666d2cad47ef055a1d7b16df4c958d7
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8e3aa68d666d2cad47ef055a1d7b16df4c958d7

Author: Wladimir J. van der Laan <laa...@gmail.com>
Date:   Tue Aug  8 15:06:21 2017 +0000

freedreno: a2xx: Implement DP2 instruction

Use DOT2ADDv instruction with 0.0f constant add.

Signed-off-by: Wladimir J. van der Laan <laa...@gmail.com>
Reviewed-by: Ilia Mirkin <imir...@alum.mit.edu>
Reviewed-by: Rob Clark <robdcl...@gmail.com>

---

 src/gallium/drivers/freedreno/a2xx/fd2_compiler.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c 
b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
index 84855a48d2..3ad47f9850 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_compiler.c
@@ -987,6 +987,24 @@ translate_trig(struct fd2_compile_context *ctx,
        add_src_reg(ctx, instr, &tmp_src);
 }
 
+static void
+translate_dp2(struct fd2_compile_context *ctx,
+               struct tgsi_full_instruction *inst,
+               unsigned opc)
+{
+       struct tgsi_src_register tmp_const;
+       struct ir2_instruction *instr;
+       /* DP2ADD c,a,b -> dot2(a,b) + c */
+       /* for c we use the constant 0.0 */
+       instr = ir2_instr_create_alu(next_exec_cf(ctx), DOT2ADDv, ~0);
+       get_immediate(ctx, &tmp_const, fui(0.0f));
+       add_dst_reg(ctx, instr, &inst->Dst[0].Register);
+       add_src_reg(ctx, instr, &tmp_const);
+       add_src_reg(ctx, instr, &inst->Src[0].Register);
+       add_src_reg(ctx, instr, &inst->Src[1].Register);
+       add_vector_clamp(inst, instr);
+}
+
 /*
  * Main part of compiler/translator:
  */
@@ -1054,6 +1072,9 @@ translate_instruction(struct fd2_compile_context *ctx,
                instr = ir2_instr_create_alu(cf, ADDv, ~0);
                add_regs_vector_2(ctx, inst, instr);
                break;
+       case TGSI_OPCODE_DP2:
+               translate_dp2(ctx, inst, opc);
+               break;
        case TGSI_OPCODE_DP3:
                instr = ir2_instr_create_alu(cf, DOT3v, ~0);
                add_regs_vector_2(ctx, inst, instr);

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