Module: Mesa
Branch: master
Commit: f882c62218fdb184c57e65b9d84b6214d8eef156
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f882c62218fdb184c57e65b9d84b6214d8eef156
Author: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Date: Fri Apr 6 12:22:02 2018 +0200
radv: add radv_clear_{cmask,dcc} helpers
They will help for DCC MSAA textures and if we support mipmaps
in the future.
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
---
src/amd/vulkan/radv_cmd_buffer.c | 8 ++------
src/amd/vulkan/radv_meta.h | 5 +++++
src/amd/vulkan/radv_meta_clear.c | 27 +++++++++++++++++++++------
src/amd/vulkan/radv_meta_fast_clear.c | 4 +---
4 files changed, 29 insertions(+), 15 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index d9f12a351e..7003818b5b 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -3617,9 +3617,7 @@ void radv_initialise_cmask(struct radv_cmd_buffer
*cmd_buffer,
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
- state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
- image->offset +
image->cmask.offset,
- image->cmask.size, value);
+ state->flush_bits |= radv_clear_cmask(cmd_buffer, image, value);
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
}
@@ -3651,9 +3649,7 @@ void radv_initialize_dcc(struct radv_cmd_buffer
*cmd_buffer,
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
- state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
- image->offset + image->dcc_offset,
- image->surface.dcc_size, value);
+ state->flush_bits |= radv_clear_dcc(cmd_buffer, image, value);
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index 9f3198e879..57b76c1326 100644
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -195,6 +195,11 @@ void radv_blit_to_prime_linear(struct radv_cmd_buffer
*cmd_buffer,
struct radv_image *image,
struct radv_image *linear_image);
+uint32_t radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *image, uint32_t value);
+uint32_t radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *image, uint32_t value);
+
/* common nir builder helpers */
#include "nir/nir_builder.h"
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 98fb8fa6a7..678de4275f 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -859,6 +859,24 @@ fail:
return res;
}
+uint32_t
+radv_clear_cmask(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *image, uint32_t value)
+{
+ return radv_fill_buffer(cmd_buffer, image->bo,
+ image->offset + image->cmask.offset,
+ image->cmask.size, value);
+}
+
+uint32_t
+radv_clear_dcc(struct radv_cmd_buffer *cmd_buffer,
+ struct radv_image *image, uint32_t value)
+{
+ return radv_fill_buffer(cmd_buffer, image->bo,
+ image->offset + image->dcc_offset,
+ image->surface.dcc_size, value);
+}
+
static void vi_get_fast_clear_parameters(VkFormat format,
const VkClearColorValue *clear_value,
uint32_t* reset_value,
@@ -1020,15 +1038,12 @@ emit_fast_color_clear(struct radv_cmd_buffer
*cmd_buffer,
&clear_value, &reset_value,
&can_avoid_fast_clear_elim);
- flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
- iview->image->offset +
iview->image->dcc_offset,
- iview->image->surface.dcc_size,
reset_value);
+ flush_bits = radv_clear_dcc(cmd_buffer, iview->image,
reset_value);
+
radv_set_dcc_need_cmask_elim_pred(cmd_buffer, iview->image,
!can_avoid_fast_clear_elim);
} else {
- flush_bits = radv_fill_buffer(cmd_buffer, iview->image->bo,
- iview->image->offset +
iview->image->cmask.offset,
- iview->image->cmask.size, 0);
+ flush_bits = radv_clear_cmask(cmd_buffer, iview->image, 0);
}
if (post_flush) {
diff --git a/src/amd/vulkan/radv_meta_fast_clear.c
b/src/amd/vulkan/radv_meta_fast_clear.c
index affecfac74..928062b5ab 100644
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -771,9 +771,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer
*cmd_buffer,
state->flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
RADV_CMD_FLAG_INV_VMEM_L1;
- state->flush_bits |= radv_fill_buffer(cmd_buffer, image->bo,
- image->offset + image->dcc_offset,
- image->surface.dcc_size,
0xffffffff);
+ state->flush_bits |= radv_clear_dcc(cmd_buffer, image, 0xffffffff);
state->flush_bits |= RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META;
_______________________________________________
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
