Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Mar 7 11:10:54 2018 +1100

    ac: make use of if/loop build helpers
    These helpers insert the basic block in the same order as they
    appear in NIR making it easier to follow LLVM IR dumps. The helpers
    also insert more useful labels onto the blocks.
    TGSI use the line number of the corresponding opcode in the TGSI
    dump as the label id, here we use the corresponding block index
    from NIR.
    Reviewed-by: Marek Olšák <marek.ol...@amd.com>
    (cherry picked from commit 99cdc019bf6fe11c135b7544ef6daf4ac964fa24)
    [Juan A. Suarez: resolve trivial conflicts]
    Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Mar 7 10:55:47 2018 +1100

    radeonsi: make use of if/loop build helpers in ac
    Reviewed-by: Marek Olšák <marek.ol...@amd.com>
    (cherry picked from commit 6e1a142863b368a032e333f09feb107241446053)

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Mar 7 10:53:34 2018 +1100

    ac: add if/loop build helpers
    These have been ported over from radeonsi.
    Reviewed-by: Marek Olšák <marek.ol...@amd.com>
    (cherry picked from commit 42627dabb4db3011825a022325be7ae9b51103d6)
    [Juan A. Suarez: resolve trivial conflicts]
    Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>

Author: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Date:   Tue Apr 10 16:00:56 2018 +0200

    radv: fix picking the method for resolve subpass
    The source and destination image parameters were swapped.
    No CTS changes on Polaris10, but I suspect this might
    fix something.
    Fixes: 2a04f5481df ("radv/meta: select resolve paths")
    Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
    Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
    (cherry picked from commit 0babc8e5d665e54783c926b89183ab9a596aa04c)
    [Juan A. Suarez: resolve trivial conflicts]
    Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>

Author: Emil Velikov <emil.veli...@collabora.com>
Date:   Wed Mar 28 18:21:59 2018 +0100

    glsl: remove unreachable assert()
    Earlier commit enforced that we'll bail out if the number of terminators
    is different than 2. With that in mind, the assert() will never trigger.
    Fixes: 56b867395de ("glsl: fix infinite loop caused by bug in loop
    unrolling pass")
    Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
    Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
    (cherry picked from commit 8eceac9de7d3cd4fddabbe61d512acfed9812169)

Author: Andres Gomez <ago...@igalia.com>
Date:   Fri Mar 2 15:02:33 2018 +0200

    mesa: adds some comments regarding MESA_GLES_VERSION_OVERRIDE usage
    Fixes: 03fd6704db9 ("mesa: Add support for a new override string
    Cc: Jordan Justen <jordan.l.jus...@intel.com>
    Cc: Ian Romanick <ian.d.roman...@intel.com>
    Signed-off-by: Andres Gomez <ago...@igalia.com>
    Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
    (cherry picked from commit 7cf3932098aba5fefaf241e35ee276b82e6e8ec7)

Author: Marek Olšák <marek.ol...@amd.com>
Date:   Tue Mar 6 18:27:30 2018 -0500

    mesa: simplify MESA_GL_VERSION_OVERRIDE behavior of API override
     - Provide a correct explanation on the envvars documentation (Ian).
     - Provide a more correct explanation on the function comments (Andres).
     - Homogenize documentation and inline comments (Emil).
     - Correct a typo (Emil).
    Fixes: 2599b92eb97 ("mesa: allow forcing >=3.1 compatibility contexts
    Cc: Jordan Justen <jordan.l.jus...@intel.com>
    Cc: Ian Romanick <ian.d.roman...@intel.com>
    Cc: Eric Engestrom <eric.engest...@imgtec.com>
    Cc: Emil Velikov <emil.veli...@collabora.com>
    Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
    (cherry picked from commit 806ab42c0f53064a774f002e311cfbb7ff10a667)

Author: Andres Gomez <ago...@igalia.com>
Date:   Fri Mar 2 15:25:32 2018 +0200

    dri_util: when overriding, always reset the core version
    This way we won't fail when validating just because we may have a non
    overriden core version that is lower than the requested one, even when
    the compat version is high enough.
    For example, running glcts from VK-GL-CTS with i965, this will
    $ MESA_GL_VERSION_OVERRIDE=4.6 ./glcts --deqp-case=KHR-GL46.info.vendor
    While, this will fail:
    Fixes: 464c56d3d5c ("dri_util: Use
    Cc: Ian Romanick <ian.d.roman...@intel.com>
    Cc: Tapani Pälli <tapani.pa...@intel.com>
    Cc: Marek Olšák <marek.ol...@amd.com>
    Signed-off-by: Andres Gomez <ago...@igalia.com>
    Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
    Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>
    (cherry picked from commit 044acd3569cbe689712be3c35544ceb7da4e5347)

Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date:   Fri Mar 23 11:05:04 2018 -0700

    nir/lower_vec_to_movs: Only coalesce if the vec had a SSA destination
    Otherwise we may end up trying to coalesce in a case such as
    ssa_1 = fadd r1, r2
    r3.x = fneg(r2);
    r3 = vec4(ssa_1, ssa_1.y, ...)
    and that would cause us to move the writes to r3 from the vec to the
    fadd which would re-order them with respect to the write from the fneg.
    In order to solve this, we just don't coalesce if the destination of the
    vec is not SSA.  We could try to get clever and still coalesce if there
    are no writes to the destination of the vec between the vec and the ALU
    source.  However, since registers only come from phi webs and indirects,
    the chances of having a vec with a register destination that is actually
    coalescable into its source is very slim.
    Shader-db results on Haswell:
        total instructions in shared programs: 13657906 -> 13659101 (<.01%)
        instructions in affected programs: 149291 -> 150486 (0.80%)
        helped: 0
        HURT: 592
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105440
    Fixes: 2458ea95c56 "nir/lower_vec_to_movs: Coalesce movs on-the-fly when 
    Reported-by: Vadym Shovkoplias <vadym.shovkopl...@globallogic.com>
    Tested-by: Vadym Shovkoplias <vadym.shovkopl...@globallogic.com>
    Reviewed-by: Matt Turner <matts...@gmail.com>
    (cherry picked from commit 800df942eadc5356840f5cbc2ceaa8a65c01ee91)

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Apr 3 11:38:13 2018 +1000

    glsl: always call do_lower_jumps() after loop unrolling
    This fixes a bug in radeonsi where LLVM cannot handle the case where
    a break exists but its not the last instruction in the block.
    LLVM would fail with:
    Terminator found in the middle of a basic block!
    LLVM ERROR: Broken function found, compilation aborted!
    Fixes: 96fe8834f539 "glsl_to_tgsi: do fewer optimizations with 
    Reviewed-by: Matt Turner <matts...@gmail.com>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105317
    (cherry picked from commit b42633db8e3711e54a5bd10495b1436b8e362801)

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Sun Apr 1 09:32:28 2018 +1000

    gallium/pipebuffer: fix parenthesis location
    Without this the return value will never get set to -1. This
    was first added in 49866c8f3457 and copied in 2b396eeed983.
    Fixes: 2b396eeed983 "gallium/pb_cache: add a copy of cache bufmgr 
independent of pb_manager"
    Reviewed-by: Marek Olšák <marek.ol...@amd.com>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102342
    (cherry picked from commit 7e9b7ec094500f1245eed518592f99244e54a753)

Author: Daniel Stone <dani...@collabora.com>
Date:   Mon Apr 2 13:20:34 2018 +0100

    st/dri: Initialise modifier to INVALID for DRI2
    When allocating a buffer for DRI2, set the modifier to INVALID to inform
    the backend that we have no supplied modifiers and it should do its own
    thing. The missed initialisation forced linear, even if the
    implementation had made other decisions.
    This resulted in VC4 DRI2 clients failing with:
      Modifier 0x0 vs. tiling (0x700000000000001) mismatch
    Signed-off-by: Daniel Stone <dani...@collabora.com>
    Reported-by: Andreas Müller <schnitzelt...@gmail.com>
    Reviewed-by: Eric Anholt <e...@anholt.net>
    Fixes: 3f8513172ff6 ("gallium/winsys/drm: introduce modifier field to 
    (cherry picked from commit 4cbecb61682a0ee426faaa03d824fc8fd7aef826)

Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date:   Fri Mar 23 09:27:55 2018 -0700

    intel/vec4: Set channel_sizes for MOV_INDIRECT sources
    Otherwise, any indirect push constant access results in an assertion
    failure when we start digging through the channel_sizes array.  This
    fixes dEQP-VK.pipeline.push_constant.graphics_pipeline.dynamic_index_vert
    on Haswell.  It should be a harmless no-op for GL since indirect push
    constants aren't used there.
    Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
    Fixes: e69e5c7006d "i965/vec4: load dvec3/4 uniforms first in the..."
    (cherry picked from commit 2b977989f3f01c186677988494bbf9b7342b31f2)

Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date:   Wed Apr 4 22:19:16 2018 +0200

    ac/nir: Add workaround for GFX9 buffer views.
    On GFX9 whether the buffer size is interpreted as elements or bytes
    depends on whether IDXEN is enabled in the instruction. If the index
    is a constant zero, LLVM optimizes IDXEN to 0.
    Now the size in elements is interpreted in bytes which of course
    results in out of bounds accesses.
    The correct fix is most likely to disable the LLVM optimization,
    but we need something to work with LLVM <= 6.0.
    radeonsi does the max between stride and element count on the CPU
    but that results in the size intrinsics returning the wrong size
    for the buffer. This would cause CTS errors for radv.
    v2: Also include the store changes.
    Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
    (backported from 4503ff760c794c3bb15b978a47c530037d56498e for 17.3)

Author: Eric Engestrom <eric.engest...@imgtec.com>
Date:   Mon Mar 26 15:11:45 2018 +0100

    gbm: remove never-implemented function
    I assume this was implemented in a previous version of that commit, but
    was removed in the version that actually landed.
    Fixes: 8430af5ebe1ee8119e14 "Add support for swrast to the DRM EGL platform"
    Cc: Giovanni Campagna <gcampa...@src.gnome.org>
    Signed-off-by: Eric Engestrom <eric.engest...@imgtec.com>
    Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
    (cherry picked from commit 431a1d12cc48060366caf49da76108cd0406b0f6)

Author: Xiong, James <james.xi...@intel.com>
Date:   Thu Apr 5 11:58:14 2018 -0700

    i965: return the fourcc saved in __DRIimage when possible
    When creating a image from a texture, the image's dri_format is
    set to the first plane's format, and used to look up for the
    fourcc. e.g. for FOURCC_NV12 texture, the dri_format is set to
    __DRI_IMAGE_FORMAT_R8, we end up with a wrong entry in function
         { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } },
    instead of the correct one:
         { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
           { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } },
    as a result, a wrong fourcc __DRI_IMAGE_FOURCC_R8 was returned.
    To fix this bug, the image inherits the texture's planar_format that
    has the original fourcc; Upon querying, if planar_format is set,
    return the saved fourcc; Otherwise fall back to the old way.
    v3: add a bug description and "cc mesa-stable" tag (Jason)
      remove redundant null pointer check (Tapani)
      squash 2 patches into one (James)
    v2: fall back to intel_lookup_fourcc() when planar_format is NULL
      (Dongwon & Matt Roper)
    Cc: mesa-sta...@lists.freedesktop.org
    Signed-off-by: Xiong, James <james.xi...@intel.com>
    Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>
    (cherry picked from commit f23b45dce3888112b7d26a623ab1280ce86533a1)

Author: Axel Davy <davyax...@gmail.com>
Date:   Thu Apr 5 23:46:48 2018 +0200

    st/nine: Do not use scratch for face register
    Scratch registers are reused every instructions.
    Since vFace is reused, a new temporary register
    should be used.
    Fixes: https://github.com/iXit/Mesa-3D/issues/311
    Signed-off-by: Axel Davy <davyax...@gmail.com>
    CC: "17.3 18.0" <mesa-sta...@lists.freedesktop.org>
    (cherry picked from commit d899826733b1f6614c913c1c216f8157bf9e297d)

Author: Axel Davy <davyax...@gmail.com>
Date:   Mon Apr 2 18:25:35 2018 +0200

    st/nine: Declare lighting consts for ff shaders
    The lighting constants were not declared previously,
    but were accessed with indirect addressing, which is
    Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=105442
    Signed-off-by: Axel Davy <davyax...@gmail.com>
    Tested-by: Dieter Nützel <die...@nuetzel-hh.de>
    CC: "17.3 18.0" <mesa-sta...@lists.freedesktop.org>
    (cherry picked from commit 39240926cd45519f35a6fa576c387f727b057aa1)

Author: Iago Toral Quiroga <ito...@igalia.com>
Date:   Mon Apr 2 11:39:41 2018 +0200

    compiler/spirv: set is_shadow for depth comparitor sampling opcodes
    From the SPIR-V spec, OpTypeImage:
    "Depth is whether or not this image is a depth image. (Note that
     whether or not depth comparisons are actually done is a property of
     the sampling opcode, not of this type declaration.)"
    The sampling opcodes that specify depth comparisons are
    OpImageSample{Proj}Dref{Explicit,Implicit}Lod, so we should set
    is_shadow only for these (we were using the deph property of the
    image until now).
     - Do the same for OpImageDrefGather.
     - Set is_shadow to false if the sampling opcode is not one of these (Jason)
     - Reuse an existing switch statement instead of adding a new one (Jason)
    Fixes crashes in:
    Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
    Cc: mesa-sta...@lists.freedesktop.org
    (cherry picked from commit 41ac0b1443ca7c8c3481eab978a41b7caba5503a)

Author: Sergii Romantsov <sergii.romant...@gmail.com>
Date:   Mon Apr 2 09:59:06 2018 +0300

    i965: Extend the negative 32-bit deltas to 64-bits
    Gen8+ use 48-bit address relocations so need to extend the sign
    to 64-bit return value. Without it we have higher bits zeroed
    and missing the negavive values.
    Haswell and older use 32-bit deltas so are unaffected by this issue.
      used int32_t fucntion parameter instead of explicit type conversion.
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101408
    Signed-off-by: Sergii Romantsov <sergii.romant...@globallogic.com>
    Tested-by: Andriy Khulap <andriy.khu...@globallogic.com>
    Tested-by: Stuart Young <cef...@gmail.com>
    Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk>
    Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
    Cc: "18.0 17.3" <mesa-sta...@lists.freedesktop.org>
    (cherry picked from commit 98b860e3115ff937152dbf4c843e1ecb9244734c)

Author: Juan A. Suarez Romero <jasua...@igalia.com>
Date:   Tue Apr 10 13:00:36 2018 +0200

    cherry-ignore: Explicit 18.0 only nominations
    These commits are explicity nominated for 18.0 only.
    Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>

Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date:   Tue Mar 20 12:12:12 2018 -0700

    nir/lower_indirect_derefs: Support interp_var_at intrinsics
    This fixes the fs-interpolateAtCentroid-block-array piglit test on i965.
    Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
    Cc: mesa-sta...@lists.freedesktop.org
    (cherry picked from commit 6018f5b07966a0f85dea1ee6775d50a8c85fdee1)

Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date:   Thu Mar 15 16:42:13 2018 -0700

    nir/vars_to_ssa: Remove copies from the correct set
    Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
    Cc: mesa-sta...@lists.freedesktop.org
    (cherry picked from commit 0517d65f9639349d626aeb2af48ba9e4e605900d)

Author: Henri Verbeet <hverb...@gmail.com>
Date:   Mon Mar 26 19:06:08 2018 +0430

    mesa: Inherit texture view multi-sample information from the original 
texture images.
    Found running "The Witness" in Wine. Without this patch, texture views 
    on multi-sample textures would have a GL_TEXTURE_SAMPLES of 0. All things
    considered such views actually work surprisingly well, but when combined 
    (plain) multi-sample textures in a framebuffer object, the resulting FBO is
    incomplete because the sample counts don't match.
    CC: <mesa-sta...@lists.freedesktop.org>
    Signed-off-by: Henri Verbeet <hverb...@gmail.com>
    Reviewed-by: Brian Paul <bri...@vmware.com>
    (cherry picked from commit 0b73c86b8030a7f7cb35fc85c83eff7f2b8c24a4)

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