Module: Mesa
Branch: master
Commit: 29a09e1d380375bd3483d52ac5efdc8b47cc9851
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=29a09e1d380375bd3483d52ac5efdc8b47cc9851
Author: Marek Olšák <marek.ol...@amd.com>
Date: Tue Mar 27 21:19:15 2018 -0400
radeonsi: don't flush HTILE if there is no HTILE clear
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Tested-by: Dieter Nützel <die...@nuetzel-hh.de>
---
src/gallium/drivers/radeonsi/si_clear.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_clear.c
b/src/gallium/drivers/radeonsi/si_clear.c
index f8136d2b2c..4e05d9bf5b 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -593,9 +593,9 @@ static void si_clear(struct pipe_context *ctx, unsigned
buffers,
*
* This hack decreases back-to-back ClearDepth performance.
*/
- if (sctx->screen->clear_db_cache_before_clear) {
+ if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
+ sctx->screen->clear_db_cache_before_clear)
sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
- }
}
si_blitter_begin(sctx, SI_CLEAR);
_______________________________________________
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
