Author: Marc Dietrich <marvi...@gmx.de>
Date:   Wed Jan 24 22:03:51 2018 +0100

    meson: fix HAVE_LLVM version define in meson build
    LLVM patch level is not included in HAVE_LLVM.
    Fixes: e6418ab1566d ("meson: build "radv" vulkan driver for radeon 
    Reviewed-by: Eric Engestrom <eric.engest...@imgtec.com>
    Reviewed-by: Dylan Baker <dylan.c.ba...@intel.com>
    Signed-off-by: Marc Dietrich <marvi...@gmx.de>
    (cherry picked from commit a2a1b0e75ef9adeb17468509c5f6331b42f6dc2e)

Author: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Date:   Wed Apr 11 21:34:43 2018 +0200

    radv: fix radv_layout_dcc_compressed() when image doesn't have DCC
    num_dcc_levels means that DCC is supported, but this doesn't
    mean that it's enabled by the driver. Instead, we should rely
    on radv_image_has_dcc().
    This fixes some multisample regressions since 0babc8e5d66
    ("radv: fix picking the method for resolve subpass") on Vega.
    This is because the resolve method changed from HW to FS, but
    those fails are totally unexpected, so there might some
    differences between Polaris and Vega here.
    Fixes: 44fcf587445 ("radv: Disable DCC for GENERAL layout and compute 
transfer dest.")
    Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
    Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
    (cherry picked from commit 9eac49246cdc501530418e8bd2a3e6d47173332b)
    [Juan A. Suarez: do not call radv_image_has_dcc(), as it is not defined]
    Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>

Author: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Date:   Tue Apr 10 16:00:56 2018 +0200

    radv: fix picking the method for resolve subpass
    The source and destination image parameters were swapped.
    No CTS changes on Polaris10, but I suspect this might
    fix something.
    Fixes: 2a04f5481df ("radv/meta: select resolve paths")
    Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
    Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
    (cherry picked from commit 0babc8e5d665e54783c926b89183ab9a596aa04c)

Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date:   Mon Apr 9 16:54:55 2018 +0200

    radv: Always reset draw user SGPRs after secondary command buffer.
    As we sometimes reset them to -1, -1 does not mean that they are
    not written by the secondary command buffer.
    Fixes: ad11fc3571 "radv: don't emit unneeded vertex state."
    Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
    (cherry picked from commit 41fbcc7901bc7a95fb7d5ccffdb3c18ba0361c40)

Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date:   Mon Apr 9 16:53:57 2018 +0200

    radv: Don't set instance count using predication.
    The packet can sometimes be skipped, but we still think the change takes 
    This just makes the packet always take effect.
    Fixes: ad11fc3571 "radv: don't emit unneeded vertex state."
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105942
    Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
    (cherry picked from commit 74b0b869ddd4dbd36482aa9bec3403d45396af2d)

Author: Andres Gomez <ago...@igalia.com>
Date:   Fri Mar 2 15:02:33 2018 +0200

    mesa: adds some comments regarding MESA_GLES_VERSION_OVERRIDE usage
    Fixes: 03fd6704db9 ("mesa: Add support for a new override string
    Cc: Jordan Justen <jordan.l.jus...@intel.com>
    Cc: Ian Romanick <ian.d.roman...@intel.com>
    Signed-off-by: Andres Gomez <ago...@igalia.com>
    Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
    (cherry picked from commit 7cf3932098aba5fefaf241e35ee276b82e6e8ec7)

Author: Marek Olšák <marek.ol...@amd.com>
Date:   Tue Mar 6 18:27:30 2018 -0500

    mesa: simplify MESA_GL_VERSION_OVERRIDE behavior of API override
     - Provide a correct explanation on the envvars documentation (Ian).
     - Provide a more correct explanation on the function comments (Andres).
     - Homogenize documentation and inline comments (Emil).
     - Correct a typo (Emil).
    Fixes: 2599b92eb97 ("mesa: allow forcing >=3.1 compatibility contexts
    Cc: Jordan Justen <jordan.l.jus...@intel.com>
    Cc: Ian Romanick <ian.d.roman...@intel.com>
    Cc: Eric Engestrom <eric.engest...@imgtec.com>
    Cc: Emil Velikov <emil.veli...@collabora.com>
    Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
    (cherry picked from commit 806ab42c0f53064a774f002e311cfbb7ff10a667)

Author: Andres Gomez <ago...@igalia.com>
Date:   Fri Mar 2 15:25:32 2018 +0200

    dri_util: when overriding, always reset the core version
    This way we won't fail when validating just because we may have a non
    overriden core version that is lower than the requested one, even when
    the compat version is high enough.
    For example, running glcts from VK-GL-CTS with i965, this will
    $ MESA_GL_VERSION_OVERRIDE=4.6 ./glcts --deqp-case=KHR-GL46.info.vendor
    While, this will fail:
    Fixes: 464c56d3d5c ("dri_util: Use
    Cc: Ian Romanick <ian.d.roman...@intel.com>
    Cc: Tapani Pälli <tapani.pa...@intel.com>
    Cc: Marek Olšák <marek.ol...@amd.com>
    Signed-off-by: Andres Gomez <ago...@igalia.com>
    Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
    Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>
    (cherry picked from commit 044acd3569cbe689712be3c35544ceb7da4e5347)

Author: Dylan Baker <dy...@pnwbakers.com>
Date:   Wed Apr 4 10:23:02 2018 -0700

    meson: fix megadriver symlinking
    Which should be relative instead of absolute.
    Fixes: f7f1b30f81e842db6057591470ce3cb6d4fb2795
           ("meson: extend install_megadrivers script to handle symmlinking")
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105567
    Signed-off-by: Dylan Baker <dylan.c.ba...@intel.com>
    Reviewed-and-Tested-by: Eric Engestrom <eric.engest...@imgtec.com>
    Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
    (cherry picked from commit 6ac87c17695ebf300a81ecc61e5703c6492b6e5c)

Author: Dylan Baker <dy...@pnwbakers.com>
Date:   Wed Apr 4 10:53:16 2018 -0700

    meson: Set .so version for xa like autotools does
    Fixes: 0ba909f0f111824223bc38563d1a6bc73e69c2cc
           ("meson: build gallium xa state tracker")
    Signed-off-by: Dylan Baker <dylan.c.ba...@intel.com>
    Reviewed-by: Eric Engestrom <eric.engest...@imgtec.com>
    Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
    (cherry picked from commit 19dbed6477525bff2918182b06bf01314f3cd5e9)

Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date:   Fri Mar 23 11:05:04 2018 -0700

    nir/lower_vec_to_movs: Only coalesce if the vec had a SSA destination
    Otherwise we may end up trying to coalesce in a case such as
    ssa_1 = fadd r1, r2
    r3.x = fneg(r2);
    r3 = vec4(ssa_1, ssa_1.y, ...)
    and that would cause us to move the writes to r3 from the vec to the
    fadd which would re-order them with respect to the write from the fneg.
    In order to solve this, we just don't coalesce if the destination of the
    vec is not SSA.  We could try to get clever and still coalesce if there
    are no writes to the destination of the vec between the vec and the ALU
    source.  However, since registers only come from phi webs and indirects,
    the chances of having a vec with a register destination that is actually
    coalescable into its source is very slim.
    Shader-db results on Haswell:
        total instructions in shared programs: 13657906 -> 13659101 (<.01%)
        instructions in affected programs: 149291 -> 150486 (0.80%)
        helped: 0
        HURT: 592
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105440
    Fixes: 2458ea95c56 "nir/lower_vec_to_movs: Coalesce movs on-the-fly when 
    Reported-by: Vadym Shovkoplias <vadym.shovkopl...@globallogic.com>
    Tested-by: Vadym Shovkoplias <vadym.shovkopl...@globallogic.com>
    Reviewed-by: Matt Turner <matts...@gmail.com>
    (cherry picked from commit 800df942eadc5356840f5cbc2ceaa8a65c01ee91)

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Apr 3 11:38:13 2018 +1000

    glsl: always call do_lower_jumps() after loop unrolling
    This fixes a bug in radeonsi where LLVM cannot handle the case where
    a break exists but its not the last instruction in the block.
    LLVM would fail with:
    Terminator found in the middle of a basic block!
    LLVM ERROR: Broken function found, compilation aborted!
    Fixes: 96fe8834f539 "glsl_to_tgsi: do fewer optimizations with 
    Reviewed-by: Matt Turner <matts...@gmail.com>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105317
    (cherry picked from commit b42633db8e3711e54a5bd10495b1436b8e362801)

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Sun Apr 1 09:32:28 2018 +1000

    gallium/pipebuffer: fix parenthesis location
    Without this the return value will never get set to -1. This
    was first added in 49866c8f3457 and copied in 2b396eeed983.
    Fixes: 2b396eeed983 "gallium/pb_cache: add a copy of cache bufmgr 
independent of pb_manager"
    Reviewed-by: Marek Olšák <marek.ol...@amd.com>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102342
    (cherry picked from commit 7e9b7ec094500f1245eed518592f99244e54a753)

Author: Daniel Stone <dani...@collabora.com>
Date:   Mon Apr 2 13:20:34 2018 +0100

    st/dri: Initialise modifier to INVALID for DRI2
    When allocating a buffer for DRI2, set the modifier to INVALID to inform
    the backend that we have no supplied modifiers and it should do its own
    thing. The missed initialisation forced linear, even if the
    implementation had made other decisions.
    This resulted in VC4 DRI2 clients failing with:
      Modifier 0x0 vs. tiling (0x700000000000001) mismatch
    Signed-off-by: Daniel Stone <dani...@collabora.com>
    Reported-by: Andreas Müller <schnitzelt...@gmail.com>
    Reviewed-by: Eric Anholt <e...@anholt.net>
    Fixes: 3f8513172ff6 ("gallium/winsys/drm: introduce modifier field to 
    (cherry picked from commit 4cbecb61682a0ee426faaa03d824fc8fd7aef826)

Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date:   Fri Mar 23 09:27:55 2018 -0700

    intel/vec4: Set channel_sizes for MOV_INDIRECT sources
    Otherwise, any indirect push constant access results in an assertion
    failure when we start digging through the channel_sizes array.  This
    fixes dEQP-VK.pipeline.push_constant.graphics_pipeline.dynamic_index_vert
    on Haswell.  It should be a harmless no-op for GL since indirect push
    constants aren't used there.
    Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
    Fixes: e69e5c7006d "i965/vec4: load dvec3/4 uniforms first in the..."
    (cherry picked from commit 2b977989f3f01c186677988494bbf9b7342b31f2)

Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date:   Wed Mar 28 23:54:40 2018 +0200

    ac/nir: Add workaround for GFX9 buffer views.
    On GFX9 whether the buffer size is interpreted as elements or bytes
    depends on whether IDXEN is enabled in the instruction. If the index
    is a constant zero, LLVM optimizes IDXEN to 0.
    Now the size in elements is interpreted in bytes which of course
    results in out of bounds accesses.
    The correct fix is most likely to disable the LLVM optimization,
    but we need something to work with LLVM <= 6.0.
    radeonsi does the max between stride and element count on the CPU
    but that results in the size intrinsics returning the wrong size
    for the buffer. This would cause CTS errors for radv.
    v2: Also include the store changes.
    Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
    Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
    (cherry picked from commit 4503ff760c794c3bb15b978a47c530037d56498e)
    [Juan A. Suarez: partially backported from 908a0cd1dbe5, a backport for
    17.3 stable branch; resolved trivial conflicts]

Author: Dylan Baker <dy...@pnwbakers.com>
Date:   Mon Mar 26 11:10:16 2018 -0700

    autotools: include meson_get_version
    Otherwise meson won't read the VERSION file and won't set a version.
    That means that pkg-config files will have version unset as well.
    Fixes: 3e9533d9b88d75d99632fa40e38cfed842d10842
           ("meson: Add script to use VERSION file for getting version")
    Signed-off-by: Dylan Baker <dylan.c.ba...@intel.com>
    Reviewed-by: Eric Engestrom <eric.engest...@imgtec.com>
    (cherry picked from commit bc2fdb9759dc702ec351a044b3fd408c0701fedb)

Author: Eric Engestrom <eric.engest...@imgtec.com>
Date:   Mon Mar 26 15:11:45 2018 +0100

    gbm: remove never-implemented function
    I assume this was implemented in a previous version of that commit, but
    was removed in the version that actually landed.
    Fixes: 8430af5ebe1ee8119e14 "Add support for swrast to the DRM EGL platform"
    Cc: Giovanni Campagna <gcampa...@src.gnome.org>
    Signed-off-by: Eric Engestrom <eric.engest...@imgtec.com>
    Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
    (cherry picked from commit 431a1d12cc48060366caf49da76108cd0406b0f6)

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Mon Mar 26 11:41:51 2018 +1100

    nir: fix crash in loop unroll corner case
    When an if nesting inside anouther if is optimised away we can
    end up with a loop terminator and following block that looks like
            if ssa_596 {
                    block block_5:
                    /* preds: block_4 */
                    vec1 32 ssa_601 = load_const (0xffffffff /* -nan */)
                    /* succs: block_8 */
            } else {
                    block block_6:
                    /* preds: block_4 */
                    /* succs: block_7 */
            block block_7:
            /* preds: block_6 */
            vec1 32 ssa_602 = phi block_6: ssa_552
            vec1 32 ssa_603 = phi block_6: ssa_553
            vec1 32 ssa_604 = iadd ssa_551, ssa_66
    The problem is the phis. Loop unrolling expects the last block in
    the loop to be empty once we splice the instructions in the last
    block into the continue branch. The problem is we cant move phis
    so here we lower the phis to regs when preparing the loop for
    unrolling. As it could be possible to have multiple additional
    blocks/ifs following the terminator we just convert all phis at
    the top level of the loop body for simplicity.
    We also add some comments to loop_prepare_for_unroll() while we
    are here.
    Fixes: 51daccb289eb "nir: add a loop unrolling pass"
    Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105670
    (cherry picked from commit 629ee690addad9b3dc8f68cfff5ae09858f31caf)

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Mon Mar 26 10:31:26 2018 +1100

    glsl: fix infinite loop caused by bug in loop unrolling pass
    Just checking for 2 jumps is not enough to be sure we can do a
    complex loop unroll. We need to make sure we also have also found
    2 loop terminators.
    Without this we were attempting to unroll a loop where the second
    jump was nested inside multiple ifs which loop analysis is unable
    to detect as a terminator. We ended up splicing out the first
    terminator but failed to actually unroll the loop, this resulted
    in the creation of a possible infinite loop.
    Fixes: 646621c66da9 "glsl: make loop unrolling more like the nir unrolling 
    Tested-by: Gert Wollny <gw.foss...@gmail.com>
    Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105670
    (cherry picked from commit 56b867395dee1a48594b27987d3bf68a4e745dda)
    Squashed with:
    glsl: remove unreachable assert()
    Earlier commit enforced that we'll bail out if the number of terminators
    is different than 2. With that in mind, the assert() will never trigger.
    Fixes: 56b867395de ("glsl: fix infinite loop caused by bug in loop
    unrolling pass")
    Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
    Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
    (cherry picked from commit 8eceac9de7d3cd4fddabbe61d512acfed9812169)

Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date:   Thu Mar 22 16:02:11 2018 +0000

    i965/perf: fix config registration when uploading to kernel
    When registring configurations to the kernel for the first time, we
    run into an issue where the id number is not properly set (we're using
    the wrong variable). As a result when trying to use that id later on,
    we get an error.
    This issue manifest itself the first time you use frameretrace after
    reboot, subsequent runs are fine.
    Fixes: 27ee83eaf7e9 ("i965: perf: add support for userspace configurations")
    Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
    Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
    (cherry picked from commit 1603ce1921a511f128025a49d055283440376231)
    [Juan A. Suarez: resolve trivial conflicts]
    Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>

Author: Juan A. Suarez Romero <jasua...@igalia.com>
Date:   Wed Apr 11 16:55:14 2018 +0200

    cherry-ignore: omx: always define ENABLE_ST_OMX_{BELLAGIO,TIZONIA}
    fixes: The commit fixes earlier commits 83d4a5d5aea5a8a05be2,
    b2f2236dc565dd1460f0 and c62cf1f165919bc74296 which did not land in
    Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>

Author: Caio Marcelo de Oliveira Filho <caio.olive...@intel.com>
Date:   Thu Mar 15 13:09:29 2018 -0700

    anv/pipeline: fail if TCS/TES compile fail
    v2: Add Fixes tag. (Lionel)
    Fixes: e50d4807a35e679 ("anv: Compile TCS/TES shaders.")
    Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
    (cherry picked from commit 318073ce660ca72b47ba83e37d1d0bc756f779b7)

Author: Juan A. Suarez Romero <jasua...@igalia.com>
Date:   Wed Apr 11 16:43:45 2018 +0200

    cherry-ignore: radv: handle exporting view index to fragment shader. (v1.1)
    fixes: The commit requieres earlier commits 639c4f2b54a6 and
    2cfba40eea4c which did not land in branch.
    Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>

Author: Juan A. Suarez Romero <jasua...@igalia.com>
Date:   Wed Apr 11 16:30:54 2018 +0200

    cherry-ignore: ac/shader: fix vertex input with components.
    fixes: The commit fixes earlier commit 1c57a6da5e3 which did not land in
    Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Mar 7 11:10:54 2018 +1100

    ac: make use of if/loop build helpers
    These helpers insert the basic block in the same order as they
    appear in NIR making it easier to follow LLVM IR dumps. The helpers
    also insert more useful labels onto the blocks.
    TGSI use the line number of the corresponding opcode in the TGSI
    dump as the label id, here we use the corresponding block index
    from NIR.
    Reviewed-by: Marek Olšák <marek.ol...@amd.com>
    (cherry picked from commit 99cdc019bf6fe11c135b7544ef6daf4ac964fa24)

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Mar 7 10:55:47 2018 +1100

    radeonsi: make use of if/loop build helpers in ac
    Reviewed-by: Marek Olšák <marek.ol...@amd.com>
    (cherry picked from commit 6e1a142863b368a032e333f09feb107241446053)

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Mar 7 10:53:34 2018 +1100

    ac: add if/loop build helpers
    These have been ported over from radeonsi.
    Reviewed-by: Marek Olšák <marek.ol...@amd.com>
    (cherry picked from commit 42627dabb4db3011825a022325be7ae9b51103d6)
    [Juan A. Suarez: resolve trivial conflicts]
    Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>

Author: Dylan Baker <dy...@pnwbakers.com>
Date:   Mon Mar 12 11:19:52 2018 -0700

    meson: don't use compiler.has_header
    Meson's compiler.has_header is completely useless, it only checks that a
    header exists, not whether it's usable. This creates problems if a
    header contains a conditional #error declaration, like so:
    > #if __x86_64__
    > # error "Doesn't work with x86_64!"
    > #endif
    Compiler.has_header will return true in this case, even when compiling
    for x86_64. This is useless.
    Instead, we'll do a compile check so that any #error declarations will
    be treated as errors, and compilation will work.
    Fixes compilation on x32 architecture.
    Gentoo Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=649746
    meson bug: https://github.com/mesonbuild/meson/issues/2246
    Signed-off-by: Dylan Baker <dylan.c.ba...@intel.com>
    Acked-by: Matt Turner <matts...@gmail.com>
    Reviewed-by: Eric Engestrom <eric.engest...@imgtec.com>
    (cherry picked from commit 8247a30838a74dcdd27cc2468bff8a3d8def640e)
    [Juan A. Suarez: resolve trivial conflicts]
    Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>

Author: Derek Foreman <der...@osg.samsung.com>
Date:   Thu Mar 22 10:20:43 2018 -0500

    egl/wayland: Make swrast display_sync the correct queue
    commit 03dd9a88b0be17ff0ce91e92f6902a9a85ba584a introduced per surface
    queues, but the display_sync for swrast_commit_backbuffer remained on
    the old queue.  This is likely to break when dispatching the correct
    queue at the top of function (which can't dispatch the sync callback
    we're waiting for).
    The easiest known reproduction case is running weston-subsurfaces under
    weston --use-pixman
    Signed-off-by: Derek Foreman <der...@osg.samsung.com>
    Reviewed-by: Daniel Stone <dani...@collabora.com>
    (cherry picked from commit aa18a63512ccfa4eb8bc5d043e8967738a465af4)

Author: Xiong, James <james.xi...@intel.com>
Date:   Thu Apr 5 11:58:14 2018 -0700

    i965: return the fourcc saved in __DRIimage when possible
    When creating a image from a texture, the image's dri_format is
    set to the first plane's format, and used to look up for the
    fourcc. e.g. for FOURCC_NV12 texture, the dri_format is set to
    __DRI_IMAGE_FORMAT_R8, we end up with a wrong entry in function
         { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } },
    instead of the correct one:
         { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
           { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } },
    as a result, a wrong fourcc __DRI_IMAGE_FOURCC_R8 was returned.
    To fix this bug, the image inherits the texture's planar_format that
    has the original fourcc; Upon querying, if planar_format is set,
    return the saved fourcc; Otherwise fall back to the old way.
    v3: add a bug description and "cc mesa-stable" tag (Jason)
      remove redundant null pointer check (Tapani)
      squash 2 patches into one (James)
    v2: fall back to intel_lookup_fourcc() when planar_format is NULL
      (Dongwon & Matt Roper)
    Cc: mesa-sta...@lists.freedesktop.org
    Signed-off-by: Xiong, James <james.xi...@intel.com>
    Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>
    (cherry picked from commit f23b45dce3888112b7d26a623ab1280ce86533a1)

Author: Axel Davy <davyax...@gmail.com>
Date:   Thu Apr 5 23:46:48 2018 +0200

    st/nine: Do not use scratch for face register
    Scratch registers are reused every instructions.
    Since vFace is reused, a new temporary register
    should be used.
    Fixes: https://github.com/iXit/Mesa-3D/issues/311
    Signed-off-by: Axel Davy <davyax...@gmail.com>
    CC: "17.3 18.0" <mesa-sta...@lists.freedesktop.org>
    (cherry picked from commit d899826733b1f6614c913c1c216f8157bf9e297d)

Author: Axel Davy <davyax...@gmail.com>
Date:   Mon Apr 2 18:25:35 2018 +0200

    st/nine: Declare lighting consts for ff shaders
    The lighting constants were not declared previously,
    but were accessed with indirect addressing, which is
    Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=105442
    Signed-off-by: Axel Davy <davyax...@gmail.com>
    Tested-by: Dieter Nützel <die...@nuetzel-hh.de>
    CC: "17.3 18.0" <mesa-sta...@lists.freedesktop.org>
    (cherry picked from commit 39240926cd45519f35a6fa576c387f727b057aa1)

Author: Iago Toral Quiroga <ito...@igalia.com>
Date:   Mon Apr 2 11:39:41 2018 +0200

    compiler/spirv: set is_shadow for depth comparitor sampling opcodes
    From the SPIR-V spec, OpTypeImage:
    "Depth is whether or not this image is a depth image. (Note that
     whether or not depth comparisons are actually done is a property of
     the sampling opcode, not of this type declaration.)"
    The sampling opcodes that specify depth comparisons are
    OpImageSample{Proj}Dref{Explicit,Implicit}Lod, so we should set
    is_shadow only for these (we were using the deph property of the
    image until now).
     - Do the same for OpImageDrefGather.
     - Set is_shadow to false if the sampling opcode is not one of these (Jason)
     - Reuse an existing switch statement instead of adding a new one (Jason)
    Fixes crashes in:
    Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
    Cc: mesa-sta...@lists.freedesktop.org
    (cherry picked from commit 41ac0b1443ca7c8c3481eab978a41b7caba5503a)

Author: Sergii Romantsov <sergii.romant...@gmail.com>
Date:   Mon Apr 2 09:59:06 2018 +0300

    i965: Extend the negative 32-bit deltas to 64-bits
    Gen8+ use 48-bit address relocations so need to extend the sign
    to 64-bit return value. Without it we have higher bits zeroed
    and missing the negavive values.
    Haswell and older use 32-bit deltas so are unaffected by this issue.
      used int32_t fucntion parameter instead of explicit type conversion.
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101408
    Signed-off-by: Sergii Romantsov <sergii.romant...@globallogic.com>
    Tested-by: Andriy Khulap <andriy.khu...@globallogic.com>
    Tested-by: Stuart Young <cef...@gmail.com>
    Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk>
    Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
    Cc: "18.0 17.3" <mesa-sta...@lists.freedesktop.org>
    (cherry picked from commit 98b860e3115ff937152dbf4c843e1ecb9244734c)

Author: Rob Clark <robdcl...@gmail.com>
Date:   Sun Apr 1 11:26:01 2018 -0400

    freedreno/a5xx: don't align height for PIPE_BUFFER
    Buffers can be large, so we probably don't want to make them all 32x
    bigger.  But they can't be rendered to (at least in GL) so we don't
    need this workaround to prevent page faults on mem<->gmem.
    Cc: "18.0" <mesa-sta...@lists.freedesktop.org>
    Signed-off-by: Rob Clark <robdcl...@gmail.com>
    (cherry picked from commit 2f175bfe5d8ca59a8a68b6d6d072cd7bf2f8baa9)

Author: Rob Clark <robdcl...@gmail.com>
Date:   Sun Apr 1 10:32:36 2018 -0400

    freedreno/a5xx: fix page faults on last level
    We could alternatively fall back to using "old style" draw's for
    mem<->gmem (ie. what <= a4xx do) when height is not aligned to 32,
    but that is somewhat more work (and not really something that could
    be applied to stable)
    Cc: "18.0" <mesa-sta...@lists.freedesktop.org>
    Signed-off-by: Rob Clark <robdcl...@gmail.com>
    (cherry picked from commit 1866f76f7bc3ec54b4e91eb7d329b2e6f7b6277c)

Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date:   Tue Mar 20 12:12:12 2018 -0700

    nir/lower_indirect_derefs: Support interp_var_at intrinsics
    This fixes the fs-interpolateAtCentroid-block-array piglit test on i965.
    Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
    Cc: mesa-sta...@lists.freedesktop.org
    (cherry picked from commit 6018f5b07966a0f85dea1ee6775d50a8c85fdee1)

Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date:   Thu Mar 15 16:42:13 2018 -0700

    nir/vars_to_ssa: Remove copies from the correct set
    Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
    Cc: mesa-sta...@lists.freedesktop.org
    (cherry picked from commit 0517d65f9639349d626aeb2af48ba9e4e605900d)

Author: Henri Verbeet <hverb...@gmail.com>
Date:   Mon Mar 26 19:06:08 2018 +0430

    mesa: Inherit texture view multi-sample information from the original 
texture images.
    Found running "The Witness" in Wine. Without this patch, texture views 
    on multi-sample textures would have a GL_TEXTURE_SAMPLES of 0. All things
    considered such views actually work surprisingly well, but when combined 
    (plain) multi-sample textures in a framebuffer object, the resulting FBO is
    incomplete because the sample counts don't match.
    CC: <mesa-sta...@lists.freedesktop.org>
    Signed-off-by: Henri Verbeet <hverb...@gmail.com>
    Reviewed-by: Brian Paul <bri...@vmware.com>
    (cherry picked from commit 0b73c86b8030a7f7cb35fc85c83eff7f2b8c24a4)

Author: Eric Engestrom <eric.engest...@imgtec.com>
Date:   Wed Mar 28 11:14:40 2018 +0100

    docs: fix 18.0 release note version
    Fixes: 839fb3a696679bfe975c2 "docs: Update 18.0.0 release notes"
    Cc: "18.0" <mesa-sta...@lists.freedesktop.org>
    Signed-off-by: Eric Engestrom <eric.engest...@imgtec.com>
    Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
    (cherry picked from commit d77844a5290948a490ce6921c1623d1dd7af6c31)

Author: Rob Clark <robdcl...@gmail.com>
Date:   Fri Mar 16 13:10:18 2018 -0400

    nir: fix per_vertex_output intrinsic
    This is supposed to have both BASE and COMPONENT but num_indices was
    inadvertantly set to 1.
    Cc: <mesa-sta...@lists.freedesktop.org>
    Signed-off-by: Rob Clark <robdcl...@gmail.com>
    Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
    (cherry picked from commit cc3a88e81dbceb12b79eb4ebe7a4ce5ba97fc291)

Author: Ian Romanick <ian.d.roman...@intel.com>
Date:   Fri Mar 23 11:46:12 2018 -0700

    i965/vec4: Fix null destination register in 3-source instructions
    A recent commit (see below) triggered some cases where conditional
    modifier propagation and dead code elimination would cause a MAD
    instruction like the following to be generated:
        mad.l.f0  null, ...
    Matt pointed out that fs_visitor::fixup_3src_null_dest() fixes cases
    like this in the scalar backend.  This commit basically ports that code
    to the vec4 backend.
    NOTE: I have sent a couple tests to the piglit list that reproduce this
    bug *without* the commit mentioned below.  This commit fixes those
    Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
    Reviewed-by: Matt Turner <matts...@gmail.com>
    Tested-by: Tapani Pälli <tapani.pa...@intel.com>
    Cc: mesa-sta...@lists.freedesktop.org
    Fixes: ee63933a7 ("nir: Distribute binary operations with constants into 
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105704
    (cherry picked from commit 91225cb33f0baede872114bd416084b3b52937a1)

Author: Eric Engestrom <eric.engest...@imgtec.com>
Date:   Wed Mar 21 17:04:06 2018 +0000

    meson/configure: detect endian.h instead of trying to guess when it's 
    Cc: Maxin B. John <maxin.j...@gmail.com>
    Cc: Khem Raj <raj.k...@gmail.com>
    Cc: Rob Herring <r...@kernel.org>
    Suggested-by: Jon Turney <jon.tur...@dronecode.org.uk>
    Signed-off-by: Eric Engestrom <eric.engest...@imgtec.com>
    Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
    Reviewed-by: Dylan Baker <dy...@pnwbakers.com>
    Cc: <mesa-sta...@lists.freedesktop.org>
    (cherry picked from commit cbee1bfb34274668a05995b9d4c78ddec9e5ea4c)
    [Juan A. Suarez: resolve trivial conflicts]
    Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>
    Squashed with:
    configure: use AC_CHECK_HEADERS to check for endian.h
    The currently we use the singular CHECK_HEADER combined with explicit
    append to the DEFINES variable. That is a legacy misnomer, since it
    requires us to add $DEFINES to every piece that we build.
    Using the plural version of the helper sets the HAVE_ macro for us, plus
    ensures it's passed to the compiler - if config.h is available in there
    (not in the case of mesa) otherwise on the command line.
    In hindsight, we should replace all the AC_CHECK_{FUNC,HEADER} instances
    with the plural version (or even the _ONCE suffixed version) and drop
    the DEFINES hacks.
    Fixes: cbee1bfb342 ("meson/configure: detect endian.h instead of trying
    to guess when it's available")
    Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105717
    Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
    Acked-by: Eric Engestrom <eric.engest...@imgtec.com>
    Tested-by: Clayton Craft <clayton.a.cr...@intel.com>
    (cherry picked from commit 5a75019ad0270a974788a9b8648ba98ff4203768)

Author: Leo Liu <leo....@amd.com>
Date:   Mon Mar 19 11:16:46 2018 -0400

    radeon/vce: move feedback command inside of destroy function
    On the CI family, firmware requires the destory command have to be the
    last command in the IB, moving feedback command after destroy is causing
    issues on CI cards, so we have to keep the previous logic that moves
    destroy back to the last command.
    But as the original issue fixed previously, with the newer family like 
    feedback command have to be included inside of the task info command along
    with destroy command.
    Fixes: 6d74cb25("radeon/vce: move destroy command before feedback command")
    Signed-off-by: Leo Liu <leo....@amd.com>
    Acked-by: Christian König <christian.koe...@amd.com>
    Cc: mesa-sta...@lists.freedesktop.org
    (cherry picked from commit c4de2f0880cfa49bd6fd3138564ee64ef4e637a1)

Author: Axel Davy <davyax...@gmail.com>
Date:   Sat Mar 10 18:49:59 2018 +0100

    st/nine: Fix non inversible matrix check
    There was a missing absolute value when
    checking if the determinant was big enough.
    Fixes: https://github.com/iXit/Mesa-3D/issues/292
    Signed-off-by: Axel Davy <davyax...@gmail.com>
    Reviewed-by: Patrick Rudolph <s...@das-labor.org>
    Tested-by: Dieter Nützel <die...@nuetzel-hh.de>
    CC: "17.3 18.0" <mesa-sta...@lists.freedesktop.org>
    (cherry picked from commit dbc24835d75466951a44b391b42e39461a6ac5a2)

Author: Axel Davy <davyax...@gmail.com>
Date:   Sat Mar 10 14:28:10 2018 +0100

    st/nine: Fixes warning about implicit conversion
    Makes the conversion explicit.
    Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=102542
    Signed-off-by: Axel Davy <davyax...@gmail.com>
    Reviewed-by: Patrick Rudolph <s...@das-labor.org>
    Tested-by: Dieter Nützel <die...@nuetzel-hh.de>
    CC: "17.3 18.0" <mesa-sta...@lists.freedesktop.org>
    (cherry picked from commit f61e9a958bd8d61cb7ca575ca987caefc6edbffd)

Author: Axel Davy <davyax...@gmail.com>
Date:   Sat Mar 10 14:23:43 2018 +0100

    st/nine: Fix bad tracking of vs textures for NINESBT_ALL
    Stateblocks with NINESBT_ALL should track all textures.
    For better performance they have a faster path which
    copies all the required.
    This path was only tracking ps textures.
    Fixes: https://github.com/iXit/Mesa-3D/issues/303
    Signed-off-by: Axel Davy <davyax...@gmail.com>
    Reviewed-by: Patrick Rudolph <s...@das-labor.org>
    Tested-by: Dieter Nützel <die...@nuetzel-hh.de>
    CC: "17.3 18.0" <mesa-sta...@lists.freedesktop.org>
    (cherry picked from commit 71eae7940ef7fa92e01cdc9afa1172f92d4b489e)

Author: Juan A. Suarez Romero <jasua...@igalia.com>
Date:   Thu Apr 12 21:48:14 2018 +0200

    cherry-ignore anv: Be more careful about fast-clear colors
    stable: There is a specific version for this patch for stable branches,
    but it is causing regressions.
    Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>

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