Module: Mesa
Branch: master
Commit: cd5ce363e3fcf975c05a5f325292e95df8322cfb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd5ce363e3fcf975c05a5f325292e95df8322cfb
Author: Nanley Chery <nanley.g.ch...@intel.com>
Date: Tue Apr 10 13:56:18 2018 -0700
i965/wm_surface_state: Use the clear address if clear_bo is non-NULL
We want to add and use a getter that turns off the indirect path by
returning zero for the clear color bo and offset.
v2: Fix usage of "clear address" in commit message (Jason).
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 17 ++++++-----------
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 8025ec128b..7cbd2d42ae 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -155,6 +155,8 @@ brw_emit_surface_state(struct brw_context *brw,
struct brw_bo *aux_bo = NULL;
struct isl_surf *aux_surf = NULL;
uint64_t aux_offset = 0;
+ struct brw_bo *clear_bo = NULL;
+ uint32_t clear_offset = 0;
if (aux_usage != ISL_AUX_USAGE_NONE) {
aux_surf = &mt->aux_buf->surf;
@@ -164,6 +166,8 @@ brw_emit_surface_state(struct brw_context *brw,
/* We only really need a clear color if we also have an auxiliary
* surface. Without one, it does nothing.
*/
+ clear_bo = mt->aux_buf->clear_color_bo;
+ clear_offset = mt->aux_buf->clear_color_offset;
clear_color = mt->fast_clear_color;
}
@@ -172,15 +176,6 @@ brw_emit_surface_state(struct brw_context *brw,
brw->isl_dev.ss.align,
surf_offset);
- bool use_clear_address = devinfo->gen >= 10 && aux_surf;
-
- struct brw_bo *clear_bo = NULL;
- uint32_t clear_offset = 0;
- if (use_clear_address) {
- clear_bo = mt->aux_buf->clear_color_bo;
- clear_offset = mt->aux_buf->clear_color_offset;
- }
-
isl_surf_fill_state(&brw->isl_dev, state, .surf = &surf, .view = &view,
.address = brw_state_reloc(&brw->batch,
*surf_offset +
brw->isl_dev.ss.addr_offset,
@@ -189,7 +184,7 @@ brw_emit_surface_state(struct brw_context *brw,
.aux_address = aux_offset,
.mocs = brw_get_bo_mocs(devinfo, mt->bo),
.clear_color = clear_color,
- .use_clear_address = use_clear_address,
+ .use_clear_address = clear_bo != NULL,
.clear_address = clear_offset,
.x_offset_sa = tile_x, .y_offset_sa = tile_y);
if (aux_surf) {
@@ -221,7 +216,7 @@ brw_emit_surface_state(struct brw_context *brw,
}
}
- if (use_clear_address) {
+ if (clear_bo != NULL) {
/* Make sure the offset is aligned with a cacheline. */
assert((clear_offset & 0x3f) == 0);
uint32_t *clear_address =
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