Module: Mesa Branch: master Commit: f575277f7e4cd3568ae2b0d8d2b0c6e0cf611d62 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f575277f7e4cd3568ae2b0d8d2b0c6e0cf611d62
Author: Jose Maria Casanova Crespo <[email protected]> Date: Thu May 3 02:18:37 2018 +0200 intel/compiler: support negate and abs of half float immediates Reviewed-by: Jason Ekstrand <[email protected]> --- src/intel/compiler/brw_shader.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index 284c2e8233..537defd05d 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -605,7 +605,8 @@ brw_negate_immediate(enum brw_reg_type type, struct brw_reg *reg) case BRW_REGISTER_TYPE_V: assert(!"unimplemented: negate UV/V immediate"); case BRW_REGISTER_TYPE_HF: - assert(!"unimplemented: negate HF immediate"); + reg->ud ^= 0x80008000; + return true; case BRW_REGISTER_TYPE_NF: unreachable("no NF immediates"); } @@ -651,7 +652,8 @@ brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg) case BRW_REGISTER_TYPE_V: assert(!"unimplemented: abs V immediate"); case BRW_REGISTER_TYPE_HF: - assert(!"unimplemented: abs HF immediate"); + reg->ud &= ~0x80008000; + return true; case BRW_REGISTER_TYPE_NF: unreachable("no NF immediates"); } _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
