Module: Mesa Branch: 18.0 Commit: 1fccd6736a1644d7d7f2d481511df1b045126435 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1fccd6736a1644d7d7f2d481511df1b045126435
Author: Marek Olšák <[email protected]> Date: Fri Apr 13 17:15:06 2018 -0400 radeonsi/gfx9: workaround for INTERP with indirect indexing and clean up the conditions. Reviewed-by: Nicolai Hähnle <[email protected]> Cc: 18.0 18.1 <[email protected]> (cherry picked from commit 6d19120da851c0d3f97376c733d674f7c8ab0457) --- src/gallium/drivers/radeonsi/si_get.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c index e38565c81a..058ebeb3bd 100644 --- a/src/gallium/drivers/radeonsi/si_get.c +++ b/src/gallium/drivers/radeonsi/si_get.c @@ -470,12 +470,19 @@ static int si_get_shader_param(struct pipe_screen* pscreen, case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: /* TODO: Indirect indexing of GS inputs is unimplemented. */ - return shader != PIPE_SHADER_GEOMETRY && - (sscreen->llvm_has_working_vgpr_indexing || - /* TCS and TES load inputs directly from LDS or - * offchip memory, so indirect indexing is trivial. */ - shader == PIPE_SHADER_TESS_CTRL || - shader == PIPE_SHADER_TESS_EVAL); + if (shader == PIPE_SHADER_GEOMETRY) + return 0; + + if (shader == PIPE_SHADER_VERTEX && + !sscreen->llvm_has_working_vgpr_indexing) + return 0; + + /* TCS and TES load inputs directly from LDS or offchip + * memory, so indirect indexing is always supported. + * PS has to support indirect indexing, because we can't + * lower that to TEMPs for INTERP instructions. + */ + return 1; case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR: return sscreen->llvm_has_working_vgpr_indexing || _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
