URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f9bd67c4bfae58f9befa2464addee3086dcab4c
Author: Kai Wasserbäch <k...@dev.carbon-project.org>
Date: Tue May 1 14:14:46 2018 +0200
opencl: autotools: Fix linking order for OpenCL target
Otherwise the build fails with an undefined reference to
clang::FrontendTimesIsEnabled.
Bugzilla: https://bugs.freedesktop.org/106209
Cc: Jan Vesely <jan.ves...@rutgers.edu>
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Kai Wasserbäch <k...@dev.carbon-project.org>
Acked-by: Jan Vesely <jan.ves...@rutgers.edu>
Tested-by: Aaron Watry <awa...@gmail.com>
Tested-by: Dieter Nützel <die...@nuetzel-hh.de>
(cherry picked from commit b691d9192c436aba5a76577b7d772a791283a2e2)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0fa8cdfd13339b8ce9c271eadf2e518ecdba64cd
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date: Sat May 12 23:56:56 2018 +0200
radv: Disable texel buffers with A2 SNORM/SSCALED/SINT for pre-vega.
The hardware always interprets the alpha as unsigned and fixing it
in the shader is going to add unacceptable overheads.
CC: 18.0 18.1 <mesa-sta...@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106480
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
(cherry picked from commit f944a59996287de85d4c6d9b7b000d25f41b1d79)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a4b915517e20baea4fce23a6b50dff79fe7f7c3
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date: Mon May 14 22:33:23 2018 +0200
radv: Fix up 2_10_10_10 alpha sign.
Pre-Vega HW always interprets the alpha for this format as unsigned,
so we have to implement a fixup to do the sign correctly for signed
formats.
v2: Improve indexing mess.
CC: 18.0 <mesa-sta...@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106480
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
(Backport of 3d4d388e392 "radv: Fix up 2_10_10_10 alpha sign.")
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b0406f465a4d2c028f7c7574299228606d4a1b1
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date: Mon May 14 03:01:21 2018 +0200
radv: Translate logic ops.
radeonsi could pass them through but the enum changed between
Gallium and Vulkan, so we have to translate.
In progress I made the register defines a bit more readable.
CC: 18.0 18.1 <mesa-sta...@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100430
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
(cherry picked from commit dd102405dea022f6c27bc42176f50f3bb2761ae6)
[Juan A. Suarez: resolve trivial conflicts]
Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>
Conflicts:
src/amd/vulkan/radv_pipeline.c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=33a8aad4591bbbac005e4ecf012c781f31311006
Author: Dave Airlie <airl...@redhat.com>
Date: Fri May 11 14:55:29 2018 +1000
radv: use compute path for multi-layer images.
I don't think the hw resolve path can't handle multi-layer images.
This fixes all the:
dEQP-VK.renderpass.multisample_resolve.layers_*
tests on my VI card.
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Cc: <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 5978d54a09e6ad151c0bd365de0e2c82bbf493d1)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a4a51bdfb32bb229dd6f3f6019f34e4c835af9f
Author: Dave Airlie <airl...@redhat.com>
Date: Fri May 11 14:54:21 2018 +1000
radv: resolve all layers in compute resolve path.
This path should iterate across all layers, I've some ideas
for doing this in a single pass, but this is simpler for now.
This passes the tests because we don't use the fragment path
unless we have DCC, and we don't have DCC on layered images.
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Cc: <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 98dbaa445a83108b59bd56e8f3224c13c36ba1d5)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a537aad110f90f740e73f829f62889282673bb5
Author: Juan A. Suarez Romero <jasua...@igalia.com>
Date: Mon May 14 10:21:09 2018 +0200
cherry-ignore: radv/resolve: do fmask decompress on all layers.
stable: The commit requires earlier commits ab0e625a671 and 62510846b6e
which did not land in branch.
Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=538022adf879c9682a9bdac75ec1a199a68b6a31
Author: Jan Vesely <jan.ves...@rutgers.edu>
Date: Thu May 10 18:29:13 2018 -0400
winsys/amdgpu: Destroy dev_hash table when the last winsys is removed.
Fixes memory leak on module unload.
CC: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.ves...@rutgers.edu>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
(cherry picked from commit 58272c1ad771802a6f15a482ae552649e9085042)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=478897779838154fca42beb297057016d403cb18
Author: Juan A. Suarez Romero <jasua...@igalia.com>
Date: Fri May 11 12:34:10 2018 +0200
cherry-ignore: mesa: revert GL_[SECONDARY_]COLOR_ARRAY_SIZE glGet type to
TYPE_INT
stable: The commit fixes earlier commit d07466fe18522 which did not land
in branch.
Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5cd442e589045449e41b318ee56ab8861deb472a
Author: Juan A. Suarez Romero <jasua...@igalia.com>
Date: Fri May 11 11:54:26 2018 +0200
cherry-ignore: mesa: fix glGetInteger/Float/etc queries for vertex arrays
attribs
stable: The commit fixes earlier commit d5f42f96e16 which did not land
in branch.
Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=81a733214a726d4f19a7b609b3f6ad2c951e2eb0
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Wed May 9 15:06:13 2018 -0700
i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL
From the bspec docs for "Indirect State Pointers Disable":
"At the completion of the post-sync operation associated with this
pipe control packet, the indirect state pointers in the hardware are
considered invalid"
So the ISP disable is a post-sync type of operation which means that it
should be combined with a CS stall. Without this, the simulator throws
an error.
Fixes: 766d801ca "anv: emit pixel scoreboard stall before ISP disable"
Fixes: f536097f6 "i965: require pixel scoreboard stall prior to ISP disable"
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
(cherry picked from commit a8a740f272a808a2694524b43fc33d2f0c0e3709)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c78a265f75eef3c4d6ac307b3dad0963dd2e9897
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue May 8 17:25:55 2018 +0100
anv: emit pixel scoreboard stall before ISP disable
We want to make sure that all indirect state data has been loaded into
the EUs before disable the pointers.
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
Fixes: 78c125af3904c ("anv/gen10: Ignore push constant packets during
context restore.")
(cherry picked from commit 766d801ca32118a722fb2e58a48ee9a96897d3b7)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=430bca7d892031f79af7339ec336d59aca706e94
Author: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Date: Tue May 1 12:32:45 2018 +0100
i965: require pixel scoreboard stall prior to ISP disable
Invalidating the indirect state pointers might affect a previously
scheduled & still running 3DPRIMITIVE (causing page fault). So stall
on pixel scoreboard before that.
v2: Fix compile issue :(
v3: Stall on pixel scoreboard
v4: Drop the post sync operation (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
Fixes: ca19ee33d7d39 ("i965/gen10: Ignore push constant packets during
context restore.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106243
(cherry picked from commit f536097f67521180dafd270b28ac9a852af9c141)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=876c7c7006eb13b91051bd5555859e5befba3e29
Author: Jan Vesely <jan.ves...@rutgers.edu>
Date: Tue May 8 01:39:04 2018 -0400
winsys/radeon: Destroy fd_hash table when the last winsys is removed.
Fixes memory leak on module unload.
v2: Use util_hash_table helper function
CC: <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
Signed-off-by: Jan Vesely <jan.ves...@rutgers.edu>
(cherry picked from commit 45dfa6f4e77fbb21f312eb6101db6c25acd4d483)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2632fc7658728dfa8b06db6c9aa54239d5bb544
Author: Jan Vesely <jan.ves...@rutgers.edu>
Date: Wed May 9 15:06:33 2018 -0400
gallium/auxiliary: Add helper function to count the number of entries in
hash table
CC: <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
Signed-off-by: Jan Vesely <jan.ves...@rutgers.edu>
(cherry picked from commit d146768d139f887105464f0db5600dd046452a8f)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=83e543e9faf041008aa68ac006c786fd84cbadf3
Author: Dave Airlie <airl...@redhat.com>
Date: Wed May 9 23:17:09 2018 +0100
r600: fix constant buffer bounds.
If you have an indirect access to a constant buffer on r600/eg
use a vertex fetch in the shader. However apps have expected
behaviour on those out of bounds accessess (even if illegal).
If the constants were being uploaded as part of a larger
upload buffer, we'd set the range of allowed access to a lot
larger than required so apps would get values back from
other parts of the upload buffer instead of the expected out
of bounds access.
This fixes rendering bugs in Trine and Witcher 1, thanks
to iive for nagging me effectively until I figured it out :-)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91808
Cc: <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <srol...@vmware.com>
(cherry picked from commit ce027ac5c798b39582288e5d7d9973b3cdda591e)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3c0ca29ff0caf8bfc2e03c65ec5c218a3b686d35
Author: Ross Burton <ross.bur...@intel.com>
Date: Wed May 9 21:48:43 2018 +0100
src/intel/Makefile.vulkan.am: add missing MKDIR_GEN
Out of tree builds can try to write into a directory that doesn't exist yet:
| Traceback (most recent call last):
| File "../../../mesa-18.0.2/src/intel/vulkan/anv_icd.py", line 46, in
<module>
| with open(args.out, 'w') as f:
| IOError: [Errno 2] No such file or directory:
'vulkan/intel_icd.x86_64.json'
| Makefile:4882: recipe for target 'vulkan/intel_icd.x86_64.json' failed
Add missing MKDIR_GEN calls to solve this.
Cc: <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Matt Turner <matts...@gmail.com>
(cherry picked from commit 1755654d9f533240dc19954b0dbccaf74e645265)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=43688542600a848892116c1feb4a10973361711b
Author: Rhys Perry <pendingchao...@gmail.com>
Date: Fri May 4 23:27:51 2018 +0100
mesa: fix error handling in get_framebuffer_parameteriv
CC: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Rhys Perry <pendingchao...@gmail.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
(cherry picked from commit 5ac16ed0476d9914927b8e7a592d8d7ac1589586)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f0c3879e6544881e6d82a129d453fedc2077449
Author: Jan Vesely <jan.ves...@rutgers.edu>
Date: Mon May 7 23:40:47 2018 -0400
pipe-loader: Free driver_name in error path
CC: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.ves...@rutgers.edu>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
(cherry picked from commit 0783399d796823fbefaab7af5551d0df90bd9dac)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eeaad26ff2b35f434c473840f5f2a1b702069d36
Author: Juan A. Suarez Romero <jasua...@igalia.com>
Date: Wed May 9 11:27:58 2018 +0200
cherry-ignore: glsl: change ast_type_qualifier bitset size to work around
GCC 5.4 bug
stable: The commit requires earlier commit ba79a90fb52 which did not
land in branch.
Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=42229106b3a2e95667be845edbc8ba5c6e8899d2
Author: Jan Vesely <jan.ves...@rutgers.edu>
Date: Mon May 7 22:54:09 2018 -0400
eg/compute: Drop reference to kernel_param bo in destructor
CC: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.ves...@rutgers.edu>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
(cherry picked from commit a9e4be9212868f619ac492aaf86b0aa68d4395c4)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c013960afd0f87d6ac076071e61d22f7c6d94f43
Author: Jan Vesely <jan.ves...@rutgers.edu>
Date: Mon May 7 22:52:19 2018 -0400
r600: Cleanup constant buffers on context destruction
CC: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Jan Vesely <jan.ves...@rutgers.edu>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
(cherry picked from commit a1e8fcce3eafa59228bb9bb50179c04f150ca9ca)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d728f903e183a686be19e22b9137b0342791c74
Author: Jan Vesely <jan.ves...@rutgers.edu>
Date: Thu May 3 23:55:00 2018 -0400
eg/compute: Drop reference on code_bo in destructor.
Signed-off-by: Jan Vesely <jan.ves...@rutgers.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
(cherry picked from commit ea1fff4416036066cff51826f95b4703d7211008)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7d0f1d676a98f0cbf47a71413db27c2fb0577f35
Author: Kenneth Graunke <kenn...@whitecape.org>
Date: Mon Apr 23 10:40:04 2018 -0700
i965: Don't leak blorp on Gen4-5.
We used to only initialize BLORP on Gen6+. When we added it on Gen4-5,
we forgot to destroy it unconditionally.
Fixes: 752d7af77a52898cebf5597def4fdd38b1d6303e (i965: Add blorp support
for gen4-5)
Reviewed-by: Matt Turner <matts...@gmail.com>
(cherry picked from commit 2dc29e095f9daffd9da722919fa08ca912ab8f04)
Squashed with:
i965: silence unused variable
Signed-off-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
Fixes: 2dc29e095f9da ("i965: Don't leak blorp on Gen4-5.")
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.olive...@intel.com>
(cherry picked from commit 3853f1c6f4b97edde22c767a80c137da6e39904a)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=54c208e48e525cd736211e9414dced3ffaddfeb2
Author: Jan Vesely <jan.ves...@rutgers.edu>
Date: Fri May 4 11:43:38 2018 -0400
clover: Add explicit virtual destructor to argument class
It is needed to destroy the v vector in scalar_argument
Fixes memory leaks on parameter set/bind.
v2: Drop redundant sclara_argument destructor
Signed-off-by: Jan Vesely <jan.ves...@rutgers.edu>
Reviewed-by: Francisco Jerez <curroje...@riseup.net>
(cherry picked from commit 2f1ad72ac17268989d4033e8e3f9460c68eae462)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=23cd0c15982f0f33f1d5c9aa05600eb9d881ba3e
Author: Neil Roberts <nrobe...@igalia.com>
Date: Wed May 2 18:10:00 2018 +0200
spirv: Apply OriginUpperLeft to FragCoord
This behaviour was changed in 1e5b09f42f694687ac. The commit message
for that says it is just a “tidy up” so my assumption is that the
behaviour change was a mistake. It’s a little hard to decipher looking
at the diff, but the previous code before that patch was:
if (builtin == SpvBuiltInFragCoord || builtin == SpvBuiltInSamplePosition)
nir_var->data.origin_upper_left = b->origin_upper_left;
if (builtin == SpvBuiltInFragCoord)
nir_var->data.pixel_center_integer = b->pixel_center_integer;
After the patch the code was:
case SpvBuiltInSamplePosition:
nir_var->data.origin_upper_left = b->origin_upper_left;
/* fallthrough */
case SpvBuiltInFragCoord:
nir_var->data.pixel_center_integer = b->pixel_center_integer;
break;
Before the patch origin_upper_left affected both builtins and
pixel_center_integer only affected FragCoord. After the patch
origin_upper_left only affects SamplePosition and pixel_center_integer
affects both variables.
This patch tries to restore the previous behaviour by changing the
code to:
case SpvBuiltInFragCoord:
nir_var->data.pixel_center_integer = b->pixel_center_integer;
/* fallthrough */
case SpvBuiltInSamplePosition:
nir_var->data.origin_upper_left = b->origin_upper_left;
break;
This change will be important for ARB_gl_spirv which is meant to
support OriginLowerLeft.
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
Reviewed-by: Anuj Phogat <anuj.pho...@gmail.com>
Fixes: 1e5b09f42f694687ac "spirv: Tidy some repeated if checks..."
(cherry picked from commit e17d0ccbbddac455e4c47f5adc2333a531fedd3e)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aecf2e13199f2c026adbd3c88ad83274892914e9
Author: Ian Romanick <ian.d.roman...@intel.com>
Date: Fri Jun 16 18:48:22 2017 -0700
mesa: Add missing support for glFogiv(GL_FOG_DISTANCE_MODE_NV)
Found by inspection, so I made a piglit test too.
Signed-off-by: Ian Romanick <ian.d.roman...@intel.com>
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
(cherry picked from commit f2db3be6200410ffd269f8789f3c97292ce03b0f)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=749626c473747db5aa3e1eb9c3f2ded98b06e5f1
Author: Deepak Rawat <dra...@vmware.com>
Date: Tue Apr 24 11:50:59 2018 -0700
egl/x11: Send invalidate to driver on copy_region path in swap_buffer
Similar to swap_available path send invalidate to the driver because
egl/X11 is not watching for for server's invalidate events. The
dri2_copy_region path is trigerred when server supports DRI2 version
minor 1.
Tested with piglit egl tests for regression.
V2: Move invalidate from dri2_copy_region to swap_buffer common.
Cc: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Deepak Rawat <dra...@vmware.com>
Signed-off-by: Thomas Hellstrom <thellst...@vmware.com>
Acked-by: Michel Dänzer <michel.daen...@amd.com>
(cherry picked from commit 9a21c96126d6a13e7b472ec622c517c0d0285ba8)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee99f7deafb33a3e5f409fd331ed3a5c6264b747
Author: Jose Maria Casanova Crespo <jmcasan...@igalia.com>
Date: Thu May 3 01:38:47 2018 +0200
intel/compiler: fix brw_imm_w for negative 16-bit integers
16-bit immediates need to replicate the 16-bit immediate value
in both words of the 32-bit value. This needs to be careful
to avoid sign-extension, which the previous implementation was
not handling properly.
For example, with the previous implementation, storing the value
-3 would generate imm.d = 0xfffffffd due to signed integer sign
extension, which is not correct. Instead, we should cast to
uint16_t, which gives us the correct result: imm.ud = 0xfffdfffd.
We only had a couple of cases hitting this path in the driver
until now, one with value -1, which would work since all bits are
one in this case, and another with value -2 in brw_clip_tri(),
which would hit the aforementioned issue (this case only affects
gen4 although we are not aware of whether this was causing an
actual bug somewhere).
v2: Make explicit uint32_t casting for left shift (Jason Ekstrand)
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
Cc: "18.0 18.1" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit f0e6dacee529661393964725bed561c45405bae4)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bbd5c75d7d6175dbdb5c44bf9b57bbbeed94a2c0
Author: Jose Maria Casanova Crespo <jmcasan...@igalia.com>
Date: Thu May 3 01:44:11 2018 +0200
intel/compiler: fix 16-bit int brw_negate_immediate and brw_abs_immediate
From Intel Skylake PRM, vol 07, "Immediate" section (page 768):
"For a word, unsigned word, or half-float immediate data,
software must replicate the same 16-bit immediate value to both
the lower word and the high word of the 32-bit immediate field
in a GEN instruction."
This fixes the int16/uint16 negate and abs immediates that weren't
taking into account the replication in lower and upper words.
v2: Integer cases are different to Float cases. (Jason Ekstrand)
Included reference to PRM (Jose Maria Casanova)
v3: Make explicit uint32_t casting for left shift (Jason Ekstrand)
Split half float implementation. (Jason Ekstrand)
Fix brw_abs_immediate (Jose Maria Casanova)
Cc: "18.0 18.1" <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
(cherry picked from commit 2a76f03c90037a8966eeb7e47d86c11a6ada9312)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ca758f6b65a571387df361a516c88e9f5940506
Author: Juan A. Suarez Romero <jasua...@igalia.com>
Date: Mon May 7 14:15:08 2018 +0200
cherry-ignore: add explicit 18.1 only nominations
Signed-off-by: Juan A. Suarez Romero <jasua...@igalia.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e97e1ea02c3f7ca84ea45fa013fb1e4569a3716
Author: Matthew Nicholls <mnicho...@feralinteractive.com>
Date: Wed May 2 14:03:52 2018 +0200
radv: fix multisample image copies
Previously before fb077b0728, the LOD parameter was being used in place of
the
sample index, which would only copy the first sample to all samples in the
destination image. After that multisample image copies wouldn't copy
anything
from my observations.
This fixes some copy_and_blit CTS tests.
v3.1: - set lod to 0 for nir_txf_ms (Samuel)
v2: - use GLSL_SAMPLER_DIM_MS instead of 2D (Samuel)
- updated commit description (Samuel)
Fix this properly by copying each sample in a separate radv_CmdDraw and
using a
pipeline with the correct rasterizationSamples for the destination image.
Cc: 18.0 18.1 <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
(cherry picked from commit 97d57ef9174111bfe1fa6f85e022af5a3cf2f1ce)
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