URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2c803be7bfb857b6846390d2aae7523319ac58e
Author: Francisco Jerez <[email protected]>
Date: Tue Apr 26 19:45:41 2016 -0700
intel/fs: Build 32-wide FS shaders.
Co-authored-by: Jason Ekstrand <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b95b0e2918c052068caeb4f6c2802ba89be043a3
Author: Jason Ekstrand <[email protected]>
Date: Fri May 18 16:39:21 2018 -0700
intel/anv,blorp,i965: Implement the SKL 16x MSAA SIMD32 workaround
Reviewed-by: Kenneth Graunke <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5e028a57bb9e0da7cd31a043859038355236095
Author: Jason Ekstrand <[email protected]>
Date: Thu May 17 23:26:02 2018 -0700
intel/fs: Add fields to wm_prog_data for SIMD32 dispatch
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bcbc7d3a1756af9f3135f53c89be253732c9e39c
Author: Francisco Jerez <[email protected]>
Date: Wed Jan 11 19:55:33 2017 -0800
intel/fs: Fix nir_intrinsic_load_helper_invocation for SIMD32.
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7144247c2c349e7013ec33cfb46eb3e84b63007a
Author: Francisco Jerez <[email protected]>
Date: Mon Jan 9 14:14:02 2017 -0800
intel/fs: Fix fs_builder::sample_mask_reg() for 32-wide FS dispatch.
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=37c1df28c993c9b065672688b20dca167eb9f04b
Author: Francisco Jerez <[email protected]>
Date: Fri Jan 13 15:33:11 2017 -0800
intel/fs: Fix Gen6+ interpolation setup for SIMD32
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e208bc3bb7f82ae1c814c9f497b17a27e3fe66b3
Author: Jason Ekstrand <[email protected]>
Date: Wed May 23 18:09:48 2018 -0700
intel/fs: Get rid of MOV_DISPATCH_TO_FLAGS
We can just emit the MOV in the two places where we use this.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e3028d8267817a5b9669bfb736722d9adb156d5
Author: Jason Ekstrand <[email protected]>
Date: Wed May 23 17:54:54 2018 -0700
intel/fs: Emit MOV_DISPATCH_TO_FLAGS once for the centroid workaround
There's no reason for us to emit it a pile of times and then have a
whole pass to clean it up. Just emit it once like we really want.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=40fe108e2b655b22b377ee92b4463a6362ba7b54
Author: Francisco Jerez <[email protected]>
Date: Fri Jan 13 15:33:45 2017 -0800
intel/fs: Generalize the unlit centroid workaround
This generalizes the unlit centroid workaround so it's less code and now
supports SIMD32.
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d381731e0db415b71ca898c68d74e0d8758e730
Author: Francisco Jerez <[email protected]>
Date: Fri Jan 13 15:32:05 2017 -0800
intel/fs: Fix sample id setup for SIMD32.
v2 (Jason Ekstrand):
- Disallow gl_SampleId in SIMD32 on gen7
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2fd0aed89a6e409377065d55bf21bb1511f5f74b
Author: Francisco Jerez <[email protected]>
Date: Fri Jan 13 17:04:23 2017 -0800
intel/fs: Fix Gen7 compressed source region alignment restriction for SIMD32
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6909aed90e75faf0d8431200c7cfd9921e55a88a
Author: Francisco Jerez <[email protected]>
Date: Fri Jan 13 15:40:38 2017 -0800
intel/fs: Implement 32-wide FS payload setup on Gen6+
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f6c4aace22aceb9089eb0e3fa297eab09dac4ce1
Author: Francisco Jerez <[email protected]>
Date: Fri Jan 13 15:36:51 2017 -0800
intel/fs: Extend thread payload layout to SIMD32
And handle 32-wide payload register reads in fetch_payload_reg().
v2 (Jason Ekstrand);
- Fix some whitespace and brace placement
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f143f70d64786a521fe57f109bff9a084cdf27f
Author: Francisco Jerez <[email protected]>
Date: Fri Jan 13 15:23:48 2017 -0800
intel/fs: Wrap FS payload register look-up in a helper function.
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d996e5b81225e84944b09f1d48b4b16e1ec4ed0c
Author: Francisco Jerez <[email protected]>
Date: Fri Jan 13 15:18:07 2017 -0800
intel/fs: Use fs_regs instead of brw_regs in the unlit centroid workaround
While we're here, we change to using horiz_offset() instead of abusing
half().
v2 (Jason Ekstrand):
- Use horiz_offset() instead of half()
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=38aee1a06d595ab4066240a5c04500dacaa01f6b
Author: Francisco Jerez <[email protected]>
Date: Fri Jan 13 14:53:00 2017 -0800
intel/fs: Simplify fs_visitor::emit_samplepos_setup
The original code manually handled splitting the MOVs to 8-wide to
handle various regioning restrictions. Now that we have a SIMD width
splitting pass that handles these things, we can just emit everything at
the full width and let the SIMD splitting pass handle it. We also now
have a useful "subscript" helper which is designed exactly for the case
where you want to take a W type and read it as a vector of Bs so we may
as well use that too.
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=244a0ff3a8b47ae1aca549a801baafbeb5712213
Author: Francisco Jerez <[email protected]>
Date: Mon Apr 25 17:02:05 2016 -0700
i965: Add plumbing for shader time in 32-wide FS dispatch mode.
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d7d652d5c02f8b68ba72490ac041d3a8235212a
Author: Francisco Jerez <[email protected]>
Date: Mon Apr 25 17:08:42 2016 -0700
intel/fs: Disable opt_sampler_eot() in 32-wide dispatch.
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=db6ca13efc1b14ee7a8d563f23c937a9a86ef569
Author: Jason Ekstrand <[email protected]>
Date: Fri May 25 22:23:30 2018 -0700
intel/fs: Emit LINE+MAC for LINTERP with unaligned coordinates
On g4x through Sandy Bridge, src1 (the coordinates) of the PLN
instruction is required to be an even register number. When it's odd
(which can happen with SIMD32), we have to emit a LINE+MAC combination
instead. Unfortunately, we can't just fall through to the gen4 case
because the input registers are still set up for PLN which lays out the
four src1 registers differently in SIMD16 than LINE.
v2 (Jason Ekstrand):
- Take advantage of both accumulators and emit LINE LINE MAC MAC
(Based on a patch from Francisco Jerez)
- Unify the gen4 and gen4x-6 cases using a loop
v3 (Jason Ekstrand):
- Don't unify gen4 with gen4x-6 as this turns out to be more fragile
than first thought without reworking the gen4 barycentric coordinate
layout.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=566e6abd6d70266aea2f43ad9fefaf7718d76c57
Author: Jason Ekstrand <[email protected]>
Date: Mon May 28 09:42:49 2018 -0700
intel/fs: Mark LINTERP opcode as writing accumulator on platforms without
PLN
When we don't have PLN (gen4 and gen11+), we implement LINTERP as either
LINE+MAC or a pair of MADs. In both cases, the accumulator is written
by the first of the two instructions and read by the second. Even
though the accumulator value isn't actually ever used from a logical
instruction perspective, it is trashed so we need to make the scheduler
aware. Otherwise, the scheduler could end up re-ordering instructions
and putting a LINTERP between another an instruction which writes the
accumulator and another which tries to use that result.
Cc: [email protected]
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=73d60455e90e14ef8618bfd09b0b4f54e1d58b48
Author: Francisco Jerez <[email protected]>
Date: Mon Apr 25 18:06:13 2016 -0700
intel/fs: Rework INTERPOLATE_AT_PER_SLOT_OFFSET
This reworks INTERPOLATE_AT_PER_SLOT_OFFSET to work more like an ALU
operation and less like a send. This is less code over-all and, as a
side-effect, it now properly handles execution groups and lowering so
SIMD32 support just falls out.
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=74b477039dbd144a3b31933a2326c32593f3ef12
Author: Jason Ekstrand <[email protected]>
Date: Thu May 17 20:51:24 2018 -0700
intel/fs: Add the group to the flag subreg number on SNB and older
We want consistent behavior in the meaning of the flag_subreg field
between SNB and IVB+.
v2 (Jason Ekstrand):
- Add some extra commentary
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2aefa5e19fc09b95affa7e61d162a6b95bfacd92
Author: Francisco Jerez <[email protected]>
Date: Mon Jan 9 16:43:24 2017 -0800
intel/fs: Fix FB read header setup for SIMD32.
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e06f5b30cc2c6b8552dcd62633ad199ce294b4ba
Author: Francisco Jerez <[email protected]>
Date: Fri Jan 13 14:25:37 2017 -0800
intel/fs: Fix logical FB write lowering for SIMD32
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ce370902d4579ba5908ff3460c07d50eb845445c
Author: Francisco Jerez <[email protected]>
Date: Fri Jan 13 14:22:19 2017 -0800
intel/fs: Fix FB write message control codegen for SIMD32.
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b788069fbb4ffe98aea52232bfd5e0200a88121
Author: Francisco Jerez <[email protected]>
Date: Fri Jan 6 14:41:27 2017 -0800
intel/fs: Don't enable dual source blend if no outputs are written
This prevents a crash in some arb_enhanced_layouts tests that would be
caused by the next commit.
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=48241c780af70f206196a4c21362efbf8c570a3b
Author: Francisco Jerez <[email protected]>
Date: Mon Apr 25 19:28:21 2016 -0700
intel/fs: Fix codegen of FS_OPCODE_SET_SAMPLE_ID for SIMD32.
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=789d20df36dfdd04fd8e9f628a26c1bab90cd037
Author: Francisco Jerez <[email protected]>
Date: Mon Apr 25 19:20:49 2016 -0700
intel/eu: Fix pixel interpolator queries for SIMD32.
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1650442026254b76f24582f4a5c567cd5f7d4a3b
Author: Francisco Jerez <[email protected]>
Date: Thu Jan 5 17:51:51 2017 -0800
intel/fs: Disable SIMD32 dispatch for fragment shaders with discard.
Current discard handling requires dedicating the second flag register to
discard. However, control-flow in SIMD32 requires both flag registers
so it's incompatible with the current discard handling. Just don't
support SIMD32+discard for now.
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1811cbdc25371362fcc7ab3dfe49bb020f7cc849
Author: Francisco Jerez <[email protected]>
Date: Mon Apr 25 17:29:57 2016 -0700
intel/fs: Disable SIMD32 dispatch on Gen4-6 with control flow
The hardware's control flow logic is 16-wide so we're out of luck
here. We could, in theory, support SIMD32 if we know the control-flow
is uniform but we don't have that information at this point.
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5b617a28e89fda62fb6cceec10686b0bb4b4fb2
Author: Jason Ekstrand <[email protected]>
Date: Mon May 21 09:51:50 2018 -0700
intel/fs: Split instructions low to high in lower_simd_width
Commit 0d905597f fixed an issue with the placement of the zip and unzip
instructions. However, as a side-effect, it reversed the order in which
we were emitting the split instructions so that they went from high
group to low instead of low to high. This is fine for most things like
texture instructions and the like but certain render target writes
really want to be emitted low to high. This commit just switches the
order back around to be low to high.
Reviewed-by: Matt Turner <[email protected]>
Fixes: 0d905597f "intel/fs: Be more explicit about our placement of [un]zip"
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b830081f0ae633911f4dd3e60f27b4ebdb67a2f
Author: Jason Ekstrand <[email protected]>
Date: Thu May 17 23:49:29 2018 -0700
intel/fs: Rework KSP data to be SIMD width-based
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d78abbef80ae79c9f81056d19eaee9a4e81aeb3
Author: Jason Ekstrand <[email protected]>
Date: Thu May 17 23:17:17 2018 -0700
intel/compiler: Add and use helpers for working with KSP indices
The pixel shader dispatch table is kind-of a confusing mess. This adds
some helpers for dealing with it and for easily extracting the correct
data from wm_prog_data.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=85750348bcd9da55c252126845445a210a79a8f9
Author: Jason Ekstrand <[email protected]>
Date: Fri May 18 13:34:33 2018 -0700
i965: Re-arrange shader kernel setup in WM state
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b6e91dd35a54297d28e086d1791a97be68c4c9e
Author: Francisco Jerez <[email protected]>
Date: Mon Apr 25 17:20:35 2016 -0700
intel/fs: Remove program key argument from generator.
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a14fb0184a0c9a5ef175bacee6e5658348ddf321
Author: Jason Ekstrand <[email protected]>
Date: Thu May 17 08:46:03 2018 -0700
intel/fs: Set up FB write message headers in the visitor
Doing instruction header setup in the generator is awful for a number
of reasons. For one, we can't schedule the header setup at all. For
another, it means lots of implied writes which the instruction scheduler
and other passes can't properly read about. The second isn't a huge
problem for FB writes since they always happen at the end. We made a
similar change to sampler handling in ff4726077d86.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dda31a7bbcd1a889e3a4098b0bdd8464e0c9d97b
Author: Francisco Jerez <[email protected]>
Date: Fri Jan 13 14:18:22 2017 -0800
intel/fs: Fix implied_mrf_writes() for headerless FB writes.
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=90643689aae96714becc5fbbd83f0a263632b404
Author: Francisco Jerez <[email protected]>
Date: Fri Jan 13 14:17:20 2017 -0800
intel/fs: Fix fs_inst::flags_written() for Gen4-5 FB writes.
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed09e7802304b7a9f9bcbde041b443b75f744ad3
Author: Francisco Jerez <[email protected]>
Date: Fri Jan 13 14:16:12 2017 -0800
intel/eu: Return new instruction to caller from brw_fb_WRITE().
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0a1c248b879af2d4726b2a2fce78e91045e6dd3
Author: Jason Ekstrand <[email protected]>
Date: Thu May 17 18:47:19 2018 -0700
intel/fs: Pull FB write implied headers from src[0]
Now that we have the implied header in src[0] for tracking purposes, we
may as well use it in the generator. This makes things a tiny bit more
general.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1cc9a9ae18a6b4133b83107a3bd8a401b3a8010
Author: Jason Ekstrand <[email protected]>
Date: Thu May 17 15:40:48 2018 -0700
intel/fs: Properly track implied header regs read by FB writes
The FB write opcode on gen4-5 does implied copies from g0 and g1 to the
message payload. With this commit, we start tracking that as part of
the IR by having the FB write read from g0-1.
Reviewed-by: Matt Turner <[email protected]>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d91fa20655bbfbd42b0ddb6acb84db7482e7ddb1
Author: Jason Ekstrand <[email protected]>
Date: Wed May 16 17:51:10 2018 -0700
intel/fs: FS_OPCODE_REP_FB_WRITE has side effects
It doesn't matter since we don't ever run replicated write shaders
through the optimizer but it's good to be complete.
Reviewed-by: Matt Turner <[email protected]>
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