Module: Mesa Branch: master Commit: 54ad9b444c8e73da498211870e785239ad3ff1aa URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=54ad9b444c8e73da498211870e785239ad3ff1aa
Author: Marek Olšák <[email protected]> Date: Thu Jul 12 00:17:02 2018 -0400 radeonsi: merge DCC/CMASK/HTILE priority flags For a later simplification. Reviewed-by: Samuel Pitoiset <[email protected]> --- src/gallium/drivers/r600/evergreen_state.c | 4 ++-- src/gallium/drivers/r600/r600_state.c | 2 +- src/gallium/drivers/radeon/radeon_winsys.h | 4 +--- src/gallium/drivers/radeonsi/si_debug.c | 4 +--- src/gallium/drivers/radeonsi/si_descriptors.c | 2 +- src/gallium/drivers/radeonsi/si_state.c | 4 ++-- 6 files changed, 8 insertions(+), 12 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 76a3e0e441..57b82e7855 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1864,7 +1864,7 @@ static void evergreen_emit_framebuffer_state(struct r600_context *rctx, struct r if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) { cmask_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, tex->cmask_buffer, RADEON_USAGE_READWRITE, - RADEON_PRIO_CMASK); + RADEON_PRIO_SEPARATE_META); } else { cmask_reloc = reloc; } @@ -2053,7 +2053,7 @@ static void evergreen_emit_db_state(struct r600_context *rctx, struct r600_atom radeon_set_context_reg(cs, R_028AC8_DB_PRELOAD_CONTROL, a->rsurf->db_preload_control); radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base); reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource, - RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE); + RADEON_USAGE_READWRITE, RADEON_PRIO_SEPARATE_META); radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); radeon_emit(cs, reloc_idx); } else { diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index d241d27d1b..9f3779f16d 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -1554,7 +1554,7 @@ static void r600_emit_db_state(struct r600_context *rctx, struct r600_atom *atom radeon_set_context_reg(cs, R_028D24_DB_HTILE_SURFACE, a->rsurf->db_htile_surface); radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, a->rsurf->db_htile_data_base); reloc_idx = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, &rtex->resource, - RADEON_USAGE_READWRITE, RADEON_PRIO_HTILE); + RADEON_USAGE_READWRITE, RADEON_PRIO_SEPARATE_META); radeon_emit(cs, PKT3(PKT3_NOP, 0, 0)); radeon_emit(cs, reloc_idx); } else { diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h index e9ae1f925c..bcd6831ed3 100644 --- a/src/gallium/drivers/radeon/radeon_winsys.h +++ b/src/gallium/drivers/radeon/radeon_winsys.h @@ -152,9 +152,7 @@ enum radeon_bo_priority { RADEON_PRIO_DEPTH_BUFFER_MSAA = 48, - RADEON_PRIO_CMASK = 52, - RADEON_PRIO_DCC, - RADEON_PRIO_HTILE, + RADEON_PRIO_SEPARATE_META = 52, RADEON_PRIO_SHADER_BINARY, /* the hw can't hide instruction cache misses */ RADEON_PRIO_SHADER_RINGS = 56, diff --git a/src/gallium/drivers/radeonsi/si_debug.c b/src/gallium/drivers/radeonsi/si_debug.c index 0e5012b9d3..50375ce7cb 100644 --- a/src/gallium/drivers/radeonsi/si_debug.c +++ b/src/gallium/drivers/radeonsi/si_debug.c @@ -511,9 +511,7 @@ static const char *priority_to_string(enum radeon_bo_priority priority) ITEM(DEPTH_BUFFER), ITEM(COLOR_BUFFER_MSAA), ITEM(DEPTH_BUFFER_MSAA), - ITEM(CMASK), - ITEM(DCC), - ITEM(HTILE), + ITEM(SEPARATE_META), ITEM(SHADER_BINARY), ITEM(SHADER_RINGS), ITEM(SCRATCH_BUFFER), diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index 83f62e4ac9..06e95e863e 100644 --- a/src/gallium/drivers/radeonsi/si_descriptors.c +++ b/src/gallium/drivers/radeonsi/si_descriptors.c @@ -269,7 +269,7 @@ static void si_sampler_view_add_buffer(struct si_context *sctx, /* Add separate DCC. */ if (tex->dcc_separate_buffer) { radeon_add_to_gfx_buffer_list_check_mem(sctx, tex->dcc_separate_buffer, - usage, RADEON_PRIO_DCC, check_mem); + usage, RADEON_PRIO_SEPARATE_META, check_mem); } } diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index a51b3739f0..7bbb1f6328 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2997,14 +2997,14 @@ static void si_emit_framebuffer_state(struct si_context *sctx) if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) { radeon_add_to_buffer_list(sctx, sctx->gfx_cs, tex->cmask_buffer, RADEON_USAGE_READWRITE, - RADEON_PRIO_CMASK); + RADEON_PRIO_SEPARATE_META); } if (tex->dcc_separate_buffer) radeon_add_to_buffer_list(sctx, sctx->gfx_cs, tex->dcc_separate_buffer, RADEON_USAGE_READWRITE, - RADEON_PRIO_DCC); + RADEON_PRIO_SEPARATE_META); /* Compute mutable surface parameters. */ cb_color_base = tex->buffer.gpu_address >> 8; _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
