Module: Mesa
Branch: master
Commit: d9526384bd98f335e421b44dc261f0b0a880a7ff
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d9526384bd98f335e421b44dc261f0b0a880a7ff

Author: Samuel Pitoiset <[email protected]>
Date:   Tue Jul 17 17:03:26 2018 +0200

radv: optimize radv_stage_flush() for pre fragment shader stages

We don't need to emit PS_PARTIAL_FLUSH for the pre fragment shader
stages (ie. geometry/tessellation). Emitting VS_PARTIAL_FLUSH
is enough for these stages. Note that PS_PARTIAL_FLUSH also
synchronizes all vertex stages.

Signed-off-by: Samuel Pitoiset <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>

---

 src/amd/vulkan/radv_cmd_buffer.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 3646c1ae89..041ebf0ca3 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1942,10 +1942,7 @@ static void radv_stage_flush(struct radv_cmd_buffer 
*cmd_buffer,
                cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
        }
 
-       if (src_stage_mask & (VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT 
|
-                             
VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
-                             VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT |
-                             VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
+       if (src_stage_mask & (VK_PIPELINE_STAGE_FRAGMENT_SHADER_BIT |
                              VK_PIPELINE_STAGE_EARLY_FRAGMENT_TESTS_BIT |
                              VK_PIPELINE_STAGE_LATE_FRAGMENT_TESTS_BIT |
                              VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT |
@@ -1956,7 +1953,10 @@ static void radv_stage_flush(struct radv_cmd_buffer 
*cmd_buffer,
                cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;
        } else if (src_stage_mask & (VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT |
                                     VK_PIPELINE_STAGE_VERTEX_INPUT_BIT |
-                                    VK_PIPELINE_STAGE_VERTEX_SHADER_BIT)) {
+                                    VK_PIPELINE_STAGE_VERTEX_SHADER_BIT |
+                                    
VK_PIPELINE_STAGE_TESSELLATION_CONTROL_SHADER_BIT |
+                                    
VK_PIPELINE_STAGE_TESSELLATION_EVALUATION_SHADER_BIT |
+                                    VK_PIPELINE_STAGE_GEOMETRY_SHADER_BIT)) {
                cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;
        }
 }

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