Module: Mesa Branch: staging/18.1 Commit: c2cf3ec7f14b16b8b41132a2a9c87db892b88c7d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2cf3ec7f14b16b8b41132a2a9c87db892b88c7d
Author: Bas Nieuwenhuizen <[email protected]> Date: Sat Jul 14 14:28:21 2018 +0200 radv: Select correct entries for binning. Overshot it by one every time. CC: <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> (cherry picked from commit 82664af6cf12b1ab7436bdcb3792315c433322d7) --- src/amd/vulkan/radv_pipeline.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 9fd53fab3c..8dd21d3b95 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -2462,7 +2462,7 @@ radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr } const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se]; - while(color_entry->bpp <= color_bytes_per_pixel) + while(color_entry[1].bpp <= color_bytes_per_pixel) ++color_entry; extent = color_entry->extent; @@ -2476,7 +2476,7 @@ radv_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCr unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples; const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se]; - while(ds_entry->bpp <= ds_bytes_per_pixel) + while(ds_entry[1].bpp <= ds_bytes_per_pixel) ++ds_entry; extent.width = MIN2(extent.width, ds_entry->extent.width); _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
