Module: Mesa Branch: master Commit: 0dd8189f159258ad8684036b0d696dbb58a268ca URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0dd8189f159258ad8684036b0d696dbb58a268ca
Author: Bas Nieuwenhuizen <[email protected]> Date: Sun Sep 16 12:28:33 2018 +0200 radv: Only allow 16 user SGPRs for compute on GFX9+. Apparently for compute there are only 16 instead of the 32 for the graphics path. Fixes dEQP-VK.binding_model.descriptorset_random.sets16.noarray.ubolimitlow.sbolimitlow.imglimitlow.noiub.comp.0 CC: <[email protected]> Reviewed-by: Samuel Pitoiset <[email protected]> --- src/amd/vulkan/radv_nir_to_llvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 968d96fc05..32d347ebd0 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -689,7 +689,7 @@ static void allocate_user_sgprs(struct radv_shader_context *ctx, if (ctx->shader_info->info.loads_push_constants) user_sgpr_count += HAVE_32BIT_POINTERS ? 1 : 2; - uint32_t available_sgprs = ctx->options->chip_class >= GFX9 ? 32 : 16; + uint32_t available_sgprs = ctx->options->chip_class >= GFX9 && stage != MESA_SHADER_COMPUTE ? 32 : 16; uint32_t remaining_sgprs = available_sgprs - user_sgpr_count; uint32_t num_desc_set = util_bitcount(ctx->shader_info->info.desc_set_used_mask); _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
