Module: Mesa
Branch: master
Commit: 77bcbe712e5224043101bdfc19aee7038bc8b0ee
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=77bcbe712e5224043101bdfc19aee7038bc8b0ee

Author: Marek Olšák <[email protected]>
Date:   Wed Oct 17 12:26:54 2018 -0400

radeonsi: clamp point size to the limit

This fixes dEQP-GLES2.functional.rasterization.limits.points.
Broken by: ea039f789d9b54e1bd1d644b6a29863ca3500314

Tested-by: Jakob Bornecrantz <[email protected]>

---

 src/gallium/drivers/radeonsi/si_get.c   | 5 +++--
 src/gallium/drivers/radeonsi/si_pipe.h  | 1 +
 src/gallium/drivers/radeonsi/si_state.c | 2 +-
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index ac302b8a94..804276b3ed 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -333,11 +333,12 @@ static float si_get_paramf(struct pipe_screen* pscreen, 
enum pipe_capf param)
        switch (param) {
        case PIPE_CAPF_MAX_LINE_WIDTH:
        case PIPE_CAPF_MAX_LINE_WIDTH_AA:
-       case PIPE_CAPF_MAX_POINT_WIDTH:
-       case PIPE_CAPF_MAX_POINT_WIDTH_AA:
                /* This depends on the quant mode, though the precise 
interactions
                 * are unknown. */
                return 2048;
+       case PIPE_CAPF_MAX_POINT_WIDTH:
+       case PIPE_CAPF_MAX_POINT_WIDTH_AA:
+               return SI_MAX_POINT_SIZE;
        case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
                return 16.0f;
        case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h 
b/src/gallium/drivers/radeonsi/si_pipe.h
index 6edc06cece..dc95afb742 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -48,6 +48,7 @@
 #define SI_BASE_VERTEX_UNKNOWN         INT_MIN
 #define SI_RESTART_INDEX_UNKNOWN       INT_MIN
 #define SI_NUM_SMOOTH_AA_SAMPLES       8
+#define SI_MAX_POINT_SIZE              2048
 #define SI_GS_PER_ES                   128
 /* Alignment for optimal CP DMA performance. */
 #define SI_CPDMA_ALIGNMENT             32
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 8b2e6e57f4..176ec74914 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -898,7 +898,7 @@ static void *si_create_rs_state(struct pipe_context *ctx,
 
        if (state->point_size_per_vertex) {
                psize_min = util_get_min_point_size(state);
-               psize_max = 8192;
+               psize_max = SI_MAX_POINT_SIZE;
        } else {
                /* Force the point size to be as if the vertex output was 
disabled. */
                psize_min = state->point_size;

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