Module: Mesa Branch: master Commit: 8f3694e1abfd702730014253af327060ac03aca1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f3694e1abfd702730014253af327060ac03aca1
Author: Eric Anholt <[email protected]> Date: Wed Feb 6 13:26:17 2019 -0800 intel: Use the NIR lowering for isign. Drops one instruction from fs-sign-int.shader_test. No change in shader-db due to it having 0 instances of sign(genIType). This may hurt isign64 if algebraic runs before int64 lowering, but I wasn't sure how to mark the algebraic opt as "every bit size but 64". v2: Update commit message about shader-db. Reviewed-by: Ian Romanick <[email protected]> (v1) --- src/intel/compiler/brw_compiler.c | 1 + src/intel/compiler/brw_fs_nir.cpp | 19 ------------------- src/intel/compiler/brw_vec4_nir.cpp | 12 ------------ 3 files changed, 1 insertion(+), 31 deletions(-) diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index fe632c5bad..35ab31df39 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -41,6 +41,7 @@ .lower_usub_borrow = true, \ .lower_fdiv = true, \ .lower_flrp64 = true, \ + .lower_isign = true, \ .lower_ldexp = true, \ .lower_cs_local_id_from_index = true, \ .lower_device_index_to_zero = true, \ diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index b7f71338f7..a24e880e58 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -875,25 +875,6 @@ fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr) break; } - case nir_op_isign: { - /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1). - * -> non-negative val generates 0x00000000. - * Predicated OR sets 1 if val is positive. - */ - uint32_t bit_size = nir_dest_bit_size(instr->dest.dest); - assert(bit_size == 32 || bit_size == 16); - - fs_reg zero = bit_size == 32 ? brw_imm_d(0) : brw_imm_w(0); - fs_reg one = bit_size == 32 ? brw_imm_d(1) : brw_imm_w(1); - fs_reg shift = bit_size == 32 ? brw_imm_d(31) : brw_imm_w(15); - - bld.CMP(bld.null_reg_d(), op[0], zero, BRW_CONDITIONAL_G); - bld.ASR(result, op[0], shift); - inst = bld.OR(result, result, one); - inst->predicate = BRW_PREDICATE_NORMAL; - break; - } - case nir_op_frcp: inst = bld.emit(SHADER_OPCODE_RCP, result, op[0]); inst->saturate = instr->dest.saturate; diff --git a/src/intel/compiler/brw_vec4_nir.cpp b/src/intel/compiler/brw_vec4_nir.cpp index 98632b5af0..d84b0f6b23 100644 --- a/src/intel/compiler/brw_vec4_nir.cpp +++ b/src/intel/compiler/brw_vec4_nir.cpp @@ -1735,18 +1735,6 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr) } break; - case nir_op_isign: - /* ASR(val, 31) -> negative val generates 0xffffffff (signed -1). - * -> non-negative val generates 0x00000000. - * Predicated OR sets 1 if val is positive. - */ - assert(nir_dest_bit_size(instr->dest.dest) < 64); - emit(CMP(dst_null_d(), op[0], brw_imm_d(0), BRW_CONDITIONAL_G)); - emit(ASR(dst, op[0], brw_imm_d(31))); - inst = emit(OR(dst, src_reg(dst), brw_imm_d(1))); - inst->predicate = BRW_PREDICATE_NORMAL; - break; - case nir_op_ishl: assert(nir_dest_bit_size(instr->dest.dest) < 64); emit(SHL(dst, op[0], op[1])); _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
