Module: Mesa Branch: master Commit: 7bc33a5cd5c2e25a7b9506c520e780cbf5b12aff URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7bc33a5cd5c2e25a7b9506c520e780cbf5b12aff
Author: Marek Olšák <[email protected]> Date: Wed Apr 17 11:17:18 2019 -0400 radeonsi/gfx9: use the correct condition for the DPBB + QUANT_MODE workaround Reviewed-by: Samuel Pitoiset <[email protected]> --- src/gallium/drivers/radeonsi/si_state_viewport.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c b/src/gallium/drivers/radeonsi/si_state_viewport.c index a9a1be73ba4..f988da4520b 100644 --- a/src/gallium/drivers/radeonsi/si_state_viewport.c +++ b/src/gallium/drivers/radeonsi/si_state_viewport.c @@ -362,11 +362,11 @@ static void si_set_viewport_states(struct pipe_context *pctx, * but also leave enough space for the guardband. * * Note that primitive binning requires QUANT_MODE == 16_8 on Vega10 - * and Raven1. What we do depends on the chip: - * - Vega10: Never use primitive binning. - * - Raven1: Always use QUANT_MODE == 16_8. + * and Raven1 for line and rectangle primitive types to work correctly. + * Always use 16_8 if primitive binning is possible to occur. */ - if (ctx->family == CHIP_RAVEN) + if ((ctx->family == CHIP_VEGA10 || ctx->family == CHIP_RAVEN) && + ctx->screen->dpbb_allowed) max_extent = 16384; /* Use QUANT_MODE == 16_8. */ /* Another constraint is that all coordinates in the viewport _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
