URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b225f1892a677d9b735782c9d6aac4ee5d33c56
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Fri Aug 30 13:49:33 2019 -0700
pan/midgard: Remove mir_opt_post_move_eliminate
This optimization depended on RA running before scheduling. It therefore
no longer applies and is now unused.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d699a17475b5d123e6a22778e8ac6e005774ce92
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Fri Aug 30 12:56:55 2019 -0700
pan/midgard: Schedule before RA
This is a tradeoff.
Scheduling before RA means we don't do RA on what-will-become pipeline
registers. Importantly, it means the scheduler is able to reorder
instructions, as registers have not been decided yet.
Unfortunately, it also complicates register spilling, since the spills
themselves won't get bundled optimally and we can only spill twice per
ALU bundle (only one spill per bundle allowed here). It also prevents us
from eliminating dead moves introduced by register allocation, as they
are not dead before RA. The shader-db regressions are from poor spilling
choices introduced by the new bundling requirements. These could be
solved by the combination of a post-scheduler (to combine adjacent
spills into bundles) with a VLIW-aware spill cost calculation.
Nevertheless, the change is small enough that I feel it's worth it to
eat a tiny shader-db regression for the sake of flexibility.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e06d90c4510eb3a8c42b0e0d1a3ebfd19830069
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Fri Aug 30 11:06:33 2019 -0700
pan/midgard: Handle fragment writeout in RA
Rather than using a pile of hacks and awkward constructs in MIR to
ensure the writeout parameter gets written into r0, let's add a
dedicated shadow register class for writeout (interfering with work
register r0) so we can express the writeout condition succintly and
directly.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=116b17d2d191892aeccf8fd5044a20f5a2d0c64f
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Fri Aug 30 14:35:01 2019 -0700
pan/midgard: Do not propagate swizzles into writeout
There's no slot for it; you'll end up writing into the void and
clobbering stuff. Don't. do it.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb3cc20f42feb4a79c35ca717d4bda2430223d78
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Fri Aug 30 11:04:52 2019 -0700
pan/midgard: Fix misc. RA issues
When running the register allocator after scheduling, the MIR looks a
little different, so we need to extend the RA to handle a few of these
extra cases correctly.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5ba016d3ab1abb9f97e7864fbe5ab96e3877ee7
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Fri Aug 30 11:03:44 2019 -0700
pan/midgard: Print MIR by the bundle
After scheduling, we still have valid MIR, but we have additional
bundling annotations which we would like to keep debug, so print these.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f42cebdd8424d3e0896bd0ddc214b2996bd07a73
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Fri Aug 30 11:02:52 2019 -0700
pan/midgard: Print branches in MIR
Rather than a vague "br.??" line, annotate the branch with its target
type (useful for disambiguating discards) and whether it was inverted.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=59f2cfcbc7d9da9b9e7c45ccc58c5cdaecbe92e8
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Fri Aug 30 11:01:57 2019 -0700
pan/midgard: Remove texture_index
This is deadcode.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=76529836ecf53c977762283cf944a5c123c2b6db
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Fri Aug 30 11:01:15 2019 -0700
pan/midgard: Cleanup fragment writeout branch
I'm not sure if this is strictly necessary but it makes debugging easier
and minimizes the diff with the experimental scheduler.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc2ba8efe96f2b44a6dc3d1e0b06c3a1ee9b8f50
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Fri Aug 30 10:53:13 2019 -0700
pan/midgard: Add scheduling barriers
Scheduling occurs on a per-block basis, strongly assuming that a given
block contains at most a single branch. This does not always map to the
source NIR control flow, particularly when discard intrinsics are
involved. The solution is to allow scheduling barriers, which will
terminate a block early in code generation and open a new block.
To facilitate this, we need to move some post-block processing to a new
pass, rather than relying hackily on the current_block pointer.
This allows us to cleanup some logic analyzing branches in other parts
of the driver us well, now that the MIR is much more well-formed.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=19bceb5812cf3056c1b5ffb3c372d3f8b9872e26
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Fri Aug 30 13:57:20 2019 -0700
pan/midgard: Track shader quadword count while scheduling
This allow multiblock blend shaders to compute constant colour offsets
correctly.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=72cbd2d4e77c782fa67b96ab12e2d2ed60cc7fb7
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Fri Aug 30 10:48:41 2019 -0700
pan/midgard: Allow NULL argument in mir_has_arg
It's sometimes convenient to call this with no instruction specified. By
definition, a missing instruction cannot reference any argument, so
let's check for NULL and shortciruit to false.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bcc59ff04df2f2270de3931aa5cf7dcda248bf6f
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Fri Aug 30 10:45:57 2019 -0700
pan/midgard: Improve mir_mask_of_read_components
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5377d702925a8a48d93d324c1a05313afad2e70a
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Fri Aug 30 10:45:08 2019 -0700
pan/midgard: Extend mir_special_index to writeout
The branch has the writeout specified in its source list, making this
special even if it's not explicitly part of r0.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b56399fcd2f074f92954fdeacf760022350aaf90
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Fri Aug 30 10:44:42 2019 -0700
pan/midgard: csel_swizzle with mir get swizzle
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=28622f90882d9e13530bea9547a0793b1f4e7236
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Fri Aug 30 10:46:17 2019 -0700
pan/midgard: Add mir_insert_instruction*scheduled helpers
In order to run register allocation after scheduling, it is sometimes
necessary to be able to insert instructions into an already-scheduled
program. This is suboptimal, since it forces us to do a worst-case
scheduling, but it is nevertheless required for correct handling of
spills/fills. Let's add helpers to insert instructions as standalone
bundles for use in spilling code.
These helpers are minimal -- they *only* work on load/store ops or
moves. They should not be used for anything but register spilling; any
other instructions should be added prior to the schedule.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e369966d7c98a1d03a82d4a964f44b47522f911
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Fri Aug 30 10:42:05 2019 -0700
pan/midgard: Track csel swizzle
While it doesn't matter with an unconditional move to the conditional
register (r31), when we try to elide that move we'll need to track the
swizzle explicitly, and there is no slot for that yet since ALU ops are
normally binary.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8eafb0b74ace2564bb02c060529f2404bd67251
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Tue Aug 27 12:20:06 2019 -0700
pan/midgard: Ensure fragment writeout is in the final block
This ensures the block only has exactly one branch, which makes
scheduling happy.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cfd5bd2c7d114dd29f5bebdd12362a416d4d3bde
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Mon Aug 26 15:28:56 2019 -0700
pan/midgard: Document Midgard scheduling requirements
Oh boy. Midgard scheduling is crazy... These are all just the
requirements, not even the algorithm yet.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6e4e36566272288bc5f618ee2b7ae677bcf87dd
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Mon Aug 26 13:59:29 2019 -0700
pan/midgard: Include condition in branch->src[0]
This will allow us to reference the condition while scheduling.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd79cddafad1894ec6f768b614bbc8f03db539f7
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Tue Aug 27 14:26:27 2019 -0700
pan/midgard: Add post-schedule iteration helpers
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f29d03a1f90a15d7b11e40af5ad41ccf93eb667f
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Tue Aug 27 13:15:12 2019 -0700
pan/midgard: Fix corner case in RA
It doesn't really matter but... meh.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d722b60191c2210fa4b12cffc60f4ad8be5f7758
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Tue Aug 27 15:51:13 2019 -0700
pan/midgard: Add OP_IS_CSEL_V helper
..to distinguish from scalar csel.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=01316719cf4494c9e354fcf7a67159ba978aa5e0
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Tue Aug 27 15:50:55 2019 -0700
pan/midgard: Expose mir_get/set_swizzle
The scheduler would like to use these.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f757425a4ec05f9fb27914bfc17661c2ea53af4
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Mon Aug 26 15:06:38 2019 -0700
pan/midgard: Extract instruction sizing helper
The scheduler shouldn't need to worry about this.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bbe29149670c06a5cb5bdbd17503aae1b1219788
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Mon Aug 26 14:49:49 2019 -0700
pan/midgard: Factor out mir_is_scalar
This helper doesn't need to be in the giant loop.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=67909c8ff288483106bea63e893752e6989eb3e3
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Fri Aug 30 13:08:16 2019 -0700
pan/midgard: Count shader-db stats by bundled instructions
This does not affect shaders in any way. Rather, it makes the shader-db
instruction count recorded in the compiler accurate with the in-order
scheduler, matching up with what we calculate from pandecode.
Though shaders are the same, instruction counts cannot be compared
across this commit for this reason.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f9dc97124d8a7ce28e208c2020048b97e4aa1db
Author: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Date: Tue Aug 27 10:38:34 2019 -0700
freedreno/ir3: Link directly to Sethi-Ullman paper
Allow a direct link to the PDF itself from the authors themselves,
rather than a paywall splash page.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
Acked-by: Rob Clark <robdcl...@chromium.org>
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