Module: Mesa
Branch: master
Commit: 7bde4ddaf723a604999feefaee30ed8aae35a830
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7bde4ddaf723a604999feefaee30ed8aae35a830

Author: Timur Kristóf <[email protected]>
Date:   Fri Sep 13 15:38:50 2019 +0200

amd/common: Add num_shared_vgprs to ac_shader_config for GFX10.

In GFX10 wave64 mode, shared VGPRs allow the two wave halves to
share some data with each other.

Signed-off-by: Timur Kristóf <[email protected]>
Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Reviewed-by: Marek Olšák <[email protected]>

---

 src/amd/common/ac_binary.c | 18 ++++++++++++++++++
 src/amd/common/ac_binary.h |  2 ++
 2 files changed, 20 insertions(+)

diff --git a/src/amd/common/ac_binary.c b/src/amd/common/ac_binary.c
index 6cf05daac55..5f92a57d7bf 100644
--- a/src/amd/common/ac_binary.c
+++ b/src/amd/common/ac_binary.c
@@ -63,11 +63,29 @@ void ac_parse_shader_binary_config(const char *data, size_t 
nbytes,
                        break;
                case R_00B02C_SPI_SHADER_PGM_RSRC2_PS:
                        conf->lds_size = MAX2(conf->lds_size, 
G_00B02C_EXTRA_LDS_SIZE(value));
+                       conf->num_shared_vgprs = 
G_00B02C_SHARED_VGPR_CNT(value);
+                       conf->rsrc2 = value;
+                       break;
+               case R_00B12C_SPI_SHADER_PGM_RSRC2_VS:
+                       conf->num_shared_vgprs = 
G_00B12C_SHARED_VGPR_CNT(value);
+                       conf->rsrc2 = value;
+                       break;
+               case R_00B22C_SPI_SHADER_PGM_RSRC2_GS:
+                       conf->num_shared_vgprs = 
G_00B22C_SHARED_VGPR_CNT(value);
+                       conf->rsrc2 = value;
+                       break;
+               case R_00B42C_SPI_SHADER_PGM_RSRC2_HS:
+                       conf->num_shared_vgprs = 
G_00B42C_SHARED_VGPR_CNT(value);
+                       conf->rsrc2 = value;
                        break;
                case R_00B84C_COMPUTE_PGM_RSRC2:
                        conf->lds_size = MAX2(conf->lds_size, 
G_00B84C_LDS_SIZE(value));
                        conf->rsrc2 = value;
                        break;
+               case R_00B8A0_COMPUTE_PGM_RSRC3:
+                       conf->num_shared_vgprs = 
G_00B8A0_SHARED_VGPR_CNT(value);
+                       conf->rsrc3 = value;
+                       break;
                case R_0286CC_SPI_PS_INPUT_ENA:
                        conf->spi_ps_input_ena = value;
                        break;
diff --git a/src/amd/common/ac_binary.h b/src/amd/common/ac_binary.h
index 1276df49369..d7dbb2db32e 100644
--- a/src/amd/common/ac_binary.h
+++ b/src/amd/common/ac_binary.h
@@ -35,6 +35,7 @@ extern "C" {
 struct ac_shader_config {
        unsigned num_sgprs;
        unsigned num_vgprs;
+       unsigned num_shared_vgprs; /* GFX10: number of VGPRs shared between 
half-waves */
        unsigned spilled_sgprs;
        unsigned spilled_vgprs;
        unsigned lds_size; /* in HW allocation units; i.e 256 bytes on SI, 512 
bytes on CI+ */
@@ -44,6 +45,7 @@ struct ac_shader_config {
        unsigned scratch_bytes_per_wave;
        unsigned rsrc1;
        unsigned rsrc2;
+       unsigned rsrc3;
 };
 
 void ac_parse_shader_binary_config(const char *data, size_t nbytes,

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