Module: Mesa Branch: master Commit: e2b9d6277e56c93092ed53cec953f7a5936197c0 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2b9d6277e56c93092ed53cec953f7a5936197c0
Author: Jonathan Marek <[email protected]> Date: Tue Jul 2 17:05:27 2019 -0400 etnaviv: blt: set TS dirty after clear RS engine does this already, it is missing for BLT engine. This fixes cases where a clear isn't immediately at the start of the frame. Signed-off-by: Jonathan Marek <[email protected]> Reviewed-by: Christian Gmeiner <[email protected]> --- src/gallium/drivers/etnaviv/etnaviv_blt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/gallium/drivers/etnaviv/etnaviv_blt.c b/src/gallium/drivers/etnaviv/etnaviv_blt.c index c3e9da846f8..ef0bbe92a8f 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_blt.c +++ b/src/gallium/drivers/etnaviv/etnaviv_blt.c @@ -252,6 +252,7 @@ etna_blit_clear_color_blt(struct pipe_context *pctx, struct pipe_surface *dst, if (surf->surf.ts_size) { ctx->framebuffer.TS_COLOR_CLEAR_VALUE = new_clear_value; surf->level->ts_valid = true; + ctx->dirty |= ETNA_DIRTY_TS | ETNA_DIRTY_DERIVE_TS; } surf->level->clear_value = new_clear_value; @@ -325,6 +326,7 @@ etna_blit_clear_zs_blt(struct pipe_context *pctx, struct pipe_surface *dst, if (surf->surf.ts_size) { ctx->framebuffer.TS_DEPTH_CLEAR_VALUE = new_clear_value; surf->level->ts_valid = true; + ctx->dirty |= ETNA_DIRTY_TS | ETNA_DIRTY_DERIVE_TS; } surf->level->clear_value = new_clear_value; _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
