Module: Mesa Branch: master Commit: ca94717035f695fd25dd07bb16167c12520d86c3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca94717035f695fd25dd07bb16167c12520d86c3
Author: Iván Briano <[email protected]> Date: Wed Oct 23 09:18:03 2019 -0700 intel/compiler: Don't change hstride if not needed Alignment requirements may have changed the horizontal stride already, so don't set it if not required to avoid breaking said requirements. Fixes several tests such as dEQP-VK.subgroups.vote.graphics.subgroupallequal_int8_t Signed-off-by: Iván Briano <[email protected]> Reviewed-by: Paulo Zanoni <[email protected]> Reviewed-by: Jason Ekstrand <[email protected]> --- src/intel/compiler/brw_eu_emit.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index ecd3c34470c..44577de62e8 100644 --- a/src/intel/compiler/brw_eu_emit.c +++ b/src/intel/compiler/brw_eu_emit.c @@ -95,14 +95,15 @@ brw_set_dest(struct brw_codegen *p, brw_inst *inst, struct brw_reg dest) else if (dest.file == BRW_GENERAL_REGISTER_FILE) assert(dest.nr < 128); - /* The hardware has a restriction where if the destination is Byte, - * the instruction needs to have a stride of 2 (except for packed byte - * MOV). This seems to be required even if the destination is the NULL - * register. + /* The hardware has a restriction where a destination of size Byte with + * a stride of 1 is only allowed for a packed byte MOV. For any other + * instruction, the stride must be at least 2, even when the destination + * is the NULL register. */ if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE && dest.nr == BRW_ARF_NULL && - type_sz(dest.type) == 1) { + type_sz(dest.type) == 1 && + dest.hstride == BRW_HORIZONTAL_STRIDE_1) { dest.hstride = BRW_HORIZONTAL_STRIDE_2; } _______________________________________________ mesa-commit mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/mesa-commit
